Chip package structure
Abstract
A chip package structure includes a substrate, a chip, a light-permeable element, a first anti-reflective layer, and an adhesive element. The chip is disposed on the substrate. The light-permeable element is disposed above the chip. The light-permeable element has a first surface and a second surface opposite to each other, and the first surface faces the chip. The first anti-reflective layer covers at least part of the first surface. The adhesive element is connected between the chip and the light-permeable element, and the adhesive element separates the chip and the light-permeable element. The adhesive element and the first anti-reflective layer are not in contact with each other.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A chip package structure, comprising:
a substrate; a chip disposed on the substrate; a light-permeable element disposed above the chip, wherein the light-permeable element includes a first surface and a second surface that are opposite to each other, and the first surface faces the chip; a first anti-reflective layer covering at least part of the first surface; a second anti-reflective layer covering the second surface; and an adhesive element connected between the chip and the light-permeable element, wherein the adhesive element separates the chip and the light-permeable element, and the adhesive element and the first anti-reflective layer are not in contact with each other.
2 . The chip package structure according to claim 1 , wherein a thickness of each of the first anti-reflective layer and the second anti-reflective layer ranges from 200 nm and 1000 nm.
3 . The chip package structure according to claim 1 , further including a plurality of metal wires, and the plurality of metal wires are electrically connected between the chip and the substrate.
4 . The chip package structure according to claim 3 , further comprising an encapsulation colloid disposed on the substrate, wherein the chip, the adhesive element, the light-permeable element, the first anti-reflective layer, and the plurality of metal wires are embedded within the encapsulation colloid, and the second surface of the light-permeable element is exposed from the encapsulation colloid.
5 . The chip package structure according to claim 1 , wherein the first anti-reflective layer forms a window, the adhesive element includes a first end and a second end, the first end is disposed in the window and directly connected to the first surface, and the second surface is connected to a surface of the chip.
6 . The chip package structure according to claim 5 , wherein a gap is formed between an edge of the window and the adhesive element, the adhesive element has an average width, and a width of the gap ranges from one-tenth to one-sixth of the average width.
7 . The chip package structure according to claim 1 , further comprising a shielding layer formed at an outer side of the first surface, wherein the adhesive element includes a first end and a second end, the first end is connected to the shielding layer, and the second end is connected to a surface of the chip.
8 . The chip package structure according to claim 7 , wherein the shielding layer and the first anti-reflective layer do not overlap with each other.
9 . The chip package structure according to claim 7 , wherein the chip includes an image sensing region, and an orthogonal projection of the shielding layer that is projected onto the first surface and an orthogonal projection of the image sensing region that is projected onto the first surface do not overlap with each other.
10 . The chip package structure according to claim 1 , further comprising a shielding layer formed at an inner side of the first surface, wherein the first anti-reflective layer forms a window, the adhesive element includes a first end and a second end, the first end is disposed within the window and directly connected to an outer side of the first surface, such that the adhesive element and the shielding layer are respectively located at two opposite sides of the first surface, and the second end is connected to a surface of the chip.Join the waitlist — get patent alerts
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