Metallic lid structure for dissipating heat generated by a thermal hot spot region of an ic structure

Abstract

An Integrated Circuit (IC) structure includes a bottom level IC die and one or more top level IC dies. A first side of the one or more top level IC dies is bonded to the bottom IC die. A supporting substrate is coupled to a second side of the one or more top level IC dies. A plurality of conductive through-substrate vias (TSVs) each extend vertically through the supporting substrate. A metallic lid structure is disposed over the supporting substrate. The metallic lid structure is thermally coupled to the conductive TSVs.

What is claimed is: 
     
         1 . A structure, comprising:
 a bottom level integrated circuit (IC) die;   one or more top level IC dies, wherein a first side of the one or more top level IC dies is bonded to the bottom IC die;   a supporting substrate coupled to a second side of the one or more top level IC dies;   a plurality of conductive through-substrate vias (TSVs) that each extend vertically through the supporting substrate; and   a metallic lid structure disposed over the supporting substrate, wherein the metallic lid structure is thermally coupled to the conductive TSVs.   
     
     
         2 . The structure of  claim 1 , wherein the supporting substrate includes a silicon substrate. 
     
     
         3 . The structure of  claim 1 , wherein:
 the bottom level IC die or the one or more top level IC dies include a thermal hot spot region that has an elevated temperature compared to a rest of the bottom level IC die or a rest of the one or more top level IC dies; and   the TSVs are vertically aligned with the thermal hot spot region.   
     
     
         4 . The structure of  claim 3 , wherein:
 the bottom level IC die or the one or more top level IC dies include a plurality of thermal hot spot regions;   the plurality of conductive TSVs include a plurality of different subsets of conductive TSVs; and   each of the subsets of conductive TSVs is vertically aligned with a respective one of the thermal hot spot regions.   
     
     
         5 . The structure of  claim 1 , further comprising a first metallization structure disposed between the supporting substrate and the metallic lid structure, wherein the first metallization structure is thermally coupled to the conductive TSVs. 
     
     
         6 . The structure of  claim 5 , further comprising:
 a thermal interface material (TIM) disposed between the first metallization structure and the metallic lid structure; and   a second metallization structure disposed between the metallic lid structure and the TIM.   
     
     
         7 . The structure of  claim 6 , wherein the TIM comprises a solder material. 
     
     
         8 . The structure of  claim 1 , wherein the one or more top level IC dies include at least a first System on a Chip (SoC) die and a second SoC die. 
     
     
         9 . The structure of  claim 1 , wherein the metallic lid structure includes a copper lid structure. 
     
     
         10 . A structure, comprising:
 one or more integrated circuit (IC) dies, wherein a first region of the one or more IC dies has a greater temperature than a second region of the one or more IC dies that neighbors the first region;   a substrate disposed over the one or more IC dies, wherein the substrate includes a plurality of through substrate vias (TSVs), and wherein a location of the TSVs is vertically aligned with a location of the first region of the one or more IC dies; and   a thermally conductive lid structure disposed over the substrate, wherein the thermally conductive lid structure is thermally coupled to the first region of the one or more IC dies at least in part through the TSVs.   
     
     
         11 . The structure of  claim 10 , further comprising:
 a metallization structure disposed between the substrate and the thermally conductive lid structure, wherein the metallization structure is in direct contact with the TSVs; and   a thermal interface material (TIM) disposed between the metallization structure and the thermally conductive lid structure.   
     
     
         12 . The structure of  claim 10 , wherein the thermally conductive lid structure includes a single block of copper. 
     
     
         13 . A method, comprising:
 forming a first dielectric layer over a first side of an Integrated Circuit (IC) structure that includes one or more IC dies;   forming a plurality of first bonding pads that each extend vertically through the first dielectric layer;   bonding a supporting substrate to the first dielectric layer, wherein the supporting substrate includes a plurality of through substrate vias (TSVs), and wherein the bonding is performed such that the TSVs are thermally coupled to the first bonding pads, respectively;   reducing a thickness of the supporting substrate from the first side until the TSVs are exposed to the first side; and   attaching a metallic lid structure to the supporting substrate such that the metallic lid structure is thermally coupled to the TSVs.   
     
     
         14 . The method of  claim 13 , wherein:
 the IC structure includes one or more thermal hot spot regions; and   the bonding is performed such that each of the one or more thermal hot spot regions is vertically aligned with a respective subset of the TSVs.   
     
     
         15 . The method of  claim 13 , further comprising, after the thickness of the supporting substrate has been reduced but before the metallic lid structure has been attached:
 forming a first metallization structure over the supporting substrate, such that the TSVs are thermally coupled to the first metallization structure; and   forming a thermal interface material (TIM) over the first metallization structure, wherein the TIM is located between the first metallization structure and the metallic lid structure after the metallic lid structure has been attached.   
     
     
         16 . The method of  claim 15 , wherein:
 a second metallization structure is formed on a second side of the metallic lid structure opposite the first side; and   the attaching of the metallic lid structure includes attaching the second metallization structure to the TIM.   
     
     
         17 . The method of  claim 13 , further comprising:
 forming a second dielectric layer over the supporting substrate; and   forming a plurality of second bonding pads in the second dielectric layer;   wherein:   the second bonding pads are thermally coupled to the TSVs; and   the bonding is performed such that the first bonding pads are bonded to the second bonding pads.   
     
     
         18 . The method of  claim 13 , wherein the IC structure includes electrical circuitry, and wherein the method further comprises: forming a plurality of conductive bumps over a second side of the IC structure opposite the first side, wherein the conductive bumps are electrically coupled to the electrical circuitry of the IC structure. 
     
     
         19 . The method of  claim 13 , wherein:
 the IC structure is a wafer level IC structure; and   the method further comprises singulating the wafer level IC structure before the metallic lid structure is attached.   
     
     
         20 . The method of  claim 13 , wherein the IC structure includes a bottom IC die and one or more top IC dies that are electrically coupled to the bottom IC die.