Interconnect structure having heat dissipation capability and method for manufacturing the same

Abstract

A semiconductor structure includes a base structure including a substrate and a device unit disposed on a front surface of the substrate, a front dielectric portion disposed on the front surface to cover the device unit, a front conductive layer disposed in the front dielectric portion and connected to the device unit, a back dielectric unit disposed on a back surface of the substrate opposite to the front surface and including at least one first part which includes a first dielectric portion having a thermal conductivity which is greater than that of the front dielectric portion, and a back conductive unit which is disposed in the back dielectric unit and connected to the device unit, and which includes at least one first conductive layer disposed in the at least one first part.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a base structure including a substrate and a device unit disposed on a front surface of the substrate;   a front dielectric portion disposed on the front surface to cover the device unit;   a front conductive layer disposed in the front dielectric portion and connected to the device unit, the front conductive layer being electrically conductive;   a back dielectric unit disposed on a back surface of the substrate opposite to the front surface and including at least one first part which includes a first dielectric portion having a thermal conductivity which is greater than that of the front dielectric portion; and   a back conductive unit disposed in the back dielectric unit and connected to the device unit, the back conductive unit including at least one first conductive layer disposed in the at least one first part, the back conductive unit being electrically conductive.   
     
     
         2 . The semiconductor structure as claimed in  claim 1 , wherein the at least one first part further includes a first liner portion which has a breakdown field which is greater than that of the first dielectric portion, and which is disposed to separate the at least one first conductive layer from the first dielectric portion. 
     
     
         3 . The semiconductor structure as claimed in  claim 1 , wherein:
 the at least one first part includes three of the first parts which are stacked on each other, and the at least one first conductive layer includes three of the first conductive layers which are respectively formed in the first parts;   a first one and a second one of the first conductive layers which are respectively proximate to and distal from the base structure, serve as a first via feature and a second via feature, respectively;   a middle one of the first conductive layers, which is connected to the first via feature and the second via feature, serves as a line feature;   each of the first via feature, the second via feature and the line feature has a first surface which is proximate to the base structure, a second surface which is distal from the base structure, and a connecting surface which is connected to the first surface and the second surface and which is covered by the first liner portion of a corresponding one of the first parts; and   the first surface of the line feature has a first connecting region which is connected to the first via feature and a first routing region which extends away from the first connecting region, and which is further covered by the first line portion of the corresponding one of the first parts.   
     
     
         4 . The semiconductor structure as claimed in  claim 3 , wherein:
 the back dielectric unit further includes three etching stop layers disposed to alternate with the first parts, each of the etching stop layers having an etching selectivity ratio different from that of the first dielectric portion of each of the first parts and having a breakdown field which is greater than that of the first dielectric portion of each of the first parts; and   the second surface of the line feature has a second connecting region which is connected to the second via feature, and a second routing region which extends away from the second connecting region and which is covered by a corresponding one of the etching stop layers.   
     
     
         5 . The semiconductor structure as claimed in  claim 2 , wherein:
 the back dielectric unit further includes at least one second part which includes a second dielectric portion and which is disposed to alternate with the at least one first part, the second dielectric portion having a breakdown field which is greater than that of the first dielectric portion; and   the back conductive unit further includes at least one second conductive layer which is disposed in the at least one second part and which is connected to the at least one first conductive layer.   
     
     
         6 . The semiconductor structure as claimed in  claim 5 , wherein one of the at least one first conductive layer and the at least one second conductive layer is configured as a line feature, and the other one of the at least one first conductive layer and the at least one second conductive layer is configured as a via feature. 
     
     
         7 . The semiconductor structure as claimed in  claim 5 , wherein the at least one second part further includes a second liner portion which is disposed to separate the at least one second conductive layer from the second dielectric portion, the second liner portion having a breakdown field which is greater than that of the first dielectric portion. 
     
     
         8 . The semiconductor structure as claimed in  claim 7 , wherein the first liner portion and the second liner portion extend toward and are connected to each other. 
     
     
         9 . A semiconductor structure, comprising:
 a base structure including a substrate;   a dielectric part disposed on the substrate and including a first region proximate to the substrate and a second region distal from the substrate, at least one of the first region and the second region having a thermal conductivity which is greater than 10 W/mK; and   a conductive layer disposed in the dielectric part, and including a via portion that is disposed in the first region and a line portion that is coupled to the via portion and that is disposed in the second region.   
     
     
         10 . The semiconductor structure as claimed in  claim 1 , wherein the base structure further includes a device unit disposed on a front surface of the substrate, the dielectric part being disposed on a back surface of the substrate opposite to the front surface. 
     
     
         11 . The semiconductor structure as claimed in  claim 9 , wherein the dielectric part further includes a liner portion which is disposed to entirely separate the conductive layer from the first region and the second region, and which has a breakdown field which is greater than that of the at least one of the first region and the second region. 
     
     
         12 . The semiconductor structure as claimed in  claim 9 , wherein the first region has a thermal conductivity which is greater than 10 W/mK, the second region having a breakdown field which is greater than that of the first region. 
     
     
         13 . The semiconductor structure as claimed in  claim 9 , wherein the second region has a thermal conductivity which is greater than  10  W/mK, the first region having a breakdown field which is greater than that of the second region. 
     
     
         14 . The semiconductor structure as claimed in  claim 9 , wherein each of the first region and the second region has a thermal conductivity which is greater than 10 W/mK. 
     
     
         15 . The semiconductor structure as claimed in  claim 9 , wherein at least one of the first region and the second region has a thermal conductivity which is greater than 100 W/mK. 
     
     
         16 . The semiconductor structure as claimed in  claim 9 , wherein the at least one of the first region and the second region is made of diamond, graphite, aluminum nitride, aluminum oxide, boron arsenide, boron carbide, beryllium oxide, silicon oxide, silicon nitride, silicon carbide, magnesium oxide, zirconium oxide, bismuth oxide, titanium oxide, gallium oxide, gallium nitride, gallium arsenide, hafnium oxide, indium antimony, graphene, hexagonal-boron nitride, beta-carbon nitride, or combinations thereof. 
     
     
         17 . The semiconductor structure as claimed in  claim 16 , wherein the dielectric part further includes a liner portion which is disposed to entirely separate the conductive layer from the first region and the second region, and which has a breakdown field which is greater than that of the at least one of the first region and the second region, the liner portion including silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, hafnium oxide, zirconium aluminum oxide, hafnium aluminum oxide, hafnium silicon oxide, beryllium oxide, boron arsenide, boron carbide, magnesium oxide, bismuth oxide, titanium oxide, gallium oxide, gallium nitride, diamond, graphite, graphene, hexagonal-boron nitride, beta-carbon nitride, or combinations thereof. 
     
     
         18 . The semiconductor structure as claimed in  claim 10 , wherein the base structure further includes a power via which is disposed in the substrate and which is coupled between the device unit and the conductive layer. 
     
     
         19 . A method for manufacturing a semiconductor structure, comprising:
 forming a base structure including a substrate;   forming a dielectric part on the substrate, the dielectric part including a first region proximate to the substrate and a second region distal from the substrate, at least one of the first region and the second region having a thermal conductivity which is greater than 10 W/mK; and   forming a conductive layer in the dielectric part, the conductive layer including a via portion which is disposed in the first region and a line portion that is coupled to the via portion and that is disposed in the second region.   
     
     
         20 . The method as claimed in  claim 1 , further comprising forming a liner portion to entirely separate the conductive layer from the first region and the second region, the liner portion having a breakdown field which is greater than that of at least one of the first region and the second region.