Exposure method of semiconductor pattern

Abstract

The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

What is claimed is: 
     
         1 . An exposure method of a semiconductor pattern, comprising:
 providing a substrate;   performing a first exposure step with a first photomask to form a first pattern in a first region on the substrate; and   performing a second exposure step with a second photomask to form a second pattern in a second region on the substrate, wherein the first pattern and the second pattern are in contact with each other and aligned with each other at an interface.   
     
     
         2 . The exposure method of a semiconductor pattern according to  claim 1 , further comprising performing a cutting step to cut the substrate into a plurality of dies, wherein the size of each die is larger than an area of the first region, and the first region is equal to a single maximum exposure range of the first photomask. 
     
     
         3 . The exposure method of a semiconductor pattern according to  claim 2 , wherein the areas of the first region And the second region Are equal, and the second region is equal to a single maximum exposure range of the second photomask. 
     
     
         4 . The exposure method of a semiconductor pattern according to  claim 3 , wherein the area of the first region is 26 mm*33 mm. 
     
     
         5 . The exposure method of a semiconductor pattern according to  claim 3 , wherein the size of each die is larger than the area of the first region. 
     
     
         6 . The exposure method of a semiconductor pattern according to  claim 1 , wherein the first pattern comprises a first edge and a second edge, and the second pattern comprises a third edge and a fourth edge. 
     
     
         7 . The exposure method of a semiconductor pattern according to  claim 1 , wherein the first edge and the third edge are in contact with each other and arranged in the same direction, and the second edge and the fourth edge are in contact with each other and arranged in the same direction. 
     
     
         8 . The exposure method of a semiconductor pattern according to  claim 1 , wherein the first pattern and the second pattern partially overlap, and the overlapping range of the first pattern and the second pattern is defined as a pattern overlapping portion. 
     
     
         9 . The exposure method of a semiconductor pattern according to  claim 8 , further comprising an optical correction step of adjusting a critical dimension of the first pattern and the second pattern in the pattern overlapping portion of the pattern. 
     
     
         10 . The exposure method of a semiconductor pattern according to  claim 8 , wherein the first region And the second region partially overlap, and the overlapping range is defined as a double exposure region. 
     
     
         11 . The exposure method of a semiconductor pattern according to  claim 10 , wherein the ratio of an area of the double exposure region to an area of the first region is less than 0.1. 
     
     
         12 . The exposure method of a semiconductor pattern according to  claim 1 , wherein the first pattern and the second pattern are in contact with each other, but the first pattern and the second pattern do not overlap each other. 
     
     
         13 . The exposure method of a semiconductor pattern according to  claim 12 , wherein the first region does not overlap with the second region, and the first region is aligned with the second region. 
     
     
         14 . The exposure method of a semiconductor pattern according to  claim 1 , wherein the first pattern and the second pattern both include a conductor pattern. 
     
     
         15 . The exposure method of a semiconductor pattern according to  claim 1 , wherein after the first exposure step with the first photomask, a plurality of first device patterns are formed on the substrate in the first region, and after the second exposure step with the second photomask, a plurality of second device patterns are formed on the substrate in the second region. 
     
     
         16 . The exposure method of a semiconductor pattern according to  claim 15 , wherein the first device patterns and the second device patterns are not in contact with each other. 
     
     
         17 . The exposure method of a semiconductor pattern according to  claim 2 , wherein a ratio of an area of the die to an area of the first region is less than 5.