Method for forming semiconductor memory structure

Abstract

A semiconductor memory structure includes a substrate, a doped region in the substrate, a stack over the substrate, a column disposed over the substrate and penetrating the stack, a ferroelectric layer, and semiconductor layer between the ferroelectric layer and the column. The stack includes a plurality of conductive layers and a plurality of insulating layer alternately stacked. The column includes an isolation structure, a source structure and a drain structure. The semiconductor layer is separated from the substrate by the ferroelectric layer.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate;   a doped region in the substrate;   a stack comprising a plurality of conductive layers and a plurality of insulating layer alternately stacked;   a column disposed over the substrate and penetrating the stack, and comprising an isolation structure, a source structure and a drain structure;   a ferroelectric layer; and   a semiconductor layer between the ferroelectric layer and the column,   wherein the semiconductor layer is separated from the substrate by the ferroelectric layer.   
     
     
         2 . The semiconductor structure of  claim 1 , the substrate comprises a first conductivity type, and the doped region comprises a second conductivity type complementary to the first conductivity type. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the stack comprises a staircase configuration. 
     
     
         4 . The semiconductor structure of  claim 1 , further comprising a dielectric structure disposed over the substrate. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein a top surface of the dielectric structure and a top surface of the stack are aligned with each other. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the column and the ferroelectric layer are offset from the doped region. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein sidewalls of the isolation structure of the column is coupled to the semiconductor layer, and a bottom of the isolation structure of the column is coupled to the ferroelectric layer. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein the doped region is in contact with a bottommost insulating layer of the plurality of insulating layers of the stack. 
     
     
         9 . A semiconductor structure, comprising:
 a substrate;   a plurality of doped regions in the substrate;   a stack comprising a plurality of conductive layers and a plurality of insulating layer alternately stacked;   a column disposed over the substrate and penetrating the stack, and comprising an isolation structure, a source structure and a drain structure;   a ferroelectric layer; and   a semiconductor layer between the ferroelectric layer and the column,   wherein the source structure and the drain structure are offset from the plurality of doped regions.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein the substrate and the plurality of doped region form a plurality of NPN junctions or a plurality of PNP junctions. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein the ferroelectric layer is between the semiconductor layer and the substrate. 
     
     
         12 . The semiconductor structure of  claim 9 , wherein a bottom surface of the ferroelectric layer is in contact with the substrate and separated from the plurality of doped regions. 
     
     
         13 . The semiconductor structure of  claim 9 , wherein a distance between two adjacent of the plurality of doped regions is greater than a width of the column. 
     
     
         14 . The semiconductor structure of  claim 9 , wherein the stack comprises a staircase configuration. 
     
     
         15 . The semiconductor structure of  claim 9 , further comprising a dielectric structure disposed over the substrate. 
     
     
         16 . The semiconductor structure of  claim 15 , wherein a top surface of the dielectric structure and a top surface of the stack are aligned with each other. 
     
     
         17 . A semiconductor structure, comprising:
 a substrate;   two doped regions in the substrate;   a plurality of conductive layers and a plurality of insulating layers alternately stacked over the substrate;   an isolation structure disposed over the substrate and penetrating the plurality of conductive layers and the plurality of insulating layers;   a source structure and a drain structure disposed over the substrate and penetrating the plurality of conductive layers and the plurality of insulating layers, wherein the source structure and the drain structure are disposed at two sides of the isolation structure;   wherein the source structure and the drain structure are separated from the two doped regions.   
     
     
         18 . The semiconductor structure of  claim 17 , further comprising a ferroelectric layer between the source structure and the plurality of conductive layers, and between the drain structure and the plurality of conductive layers. 
     
     
         19 . The semiconductor structure of  claim 18 , further comprising a semiconductor layer between the ferroelectric layer and source structure, and between the ferroelectric layer and the drain structure. 
     
     
         20 . The semiconductor structure of  claim 17 , wherein the substrate and the two doped regions form an NPN junction or a PNP junction.