Semiconductor package including multiple chip structures

Abstract

A semiconductor package may include vertically-stacked two or more chip structures, each of which includes first and second chips stacked. Each of the first and second chips may include a substrate, a via pattern penetrating through the substrate, an integrated circuit and a first pad on an active surface of the substrate, and a second pad on an inactive surface of the substrate. The first chip may further include a sub-pad between the via pattern and the second pad. In the second chip, the second pad may be directly coupled to the via pattern. The chip structures may be provided such that the active surfaces face each other, the first pads are directly bonded to each other, and the second pads are directly bonded to each other.

1 . A semiconductor package comprising two chip structures which are vertically stacked,
 wherein each of the chip structures comprises a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip,   wherein the first semiconductor chip comprises:
 a first semiconductor substrate; 
 a first penetration via penetrating through the first semiconductor substrate; 
 a first integrated circuit on a first active surface of the first semiconductor substrate; 
 a first pad on the first active surface of the first semiconductor substrate; 
 a second pad on a first inactive surface of the first semiconductor substrate; and 
 a sub-pad between the first penetration via and the second pad, 
   wherein the second semiconductor chip comprises:
 a second semiconductor substrate; 
 a second penetration via penetrating through a second semiconductor substrate; 
 a second integrated circuit on a second active surface of the second semiconductor substrate; 
 a third pad on the second active surface of the second semiconductor substrate; and 
 a fourth pad on a second inactive surface of the second semiconductor substrate and directly coupled to the second penetration via, 
   wherein the first active surface faces the second active surface,   wherein the first pad is directly bonded to the third pad,   wherein the fourth pad of a lower one of the chip structures is directly bonded to the second pad of an upper one of the chip structures, and   wherein a distance from the first inactive surface to a bottom surface of the second pad is greater than a distance from the second inactive surface to a top surface of the fourth pad.   
     
     
         2 . The semiconductor package of  claim 1 , further comprising a third semiconductor chip disposed on a bottom surface of the lower one of the chip structures,
 wherein the third semiconductor chip comprises a third integrated circuit on a third active surface of a third semiconductor substrate and a fifth pad on a third inactive surface of the third semiconductor substrate,   wherein a width of the third semiconductor chip is greater than a width of the chip structures,   wherein the first inactive surface of the lower one of the chip structures faces the third inactive surface, and   wherein the second pad of the lower one of the chip structures is directly bonded to the fifth pad.   
     
     
         3 . The semiconductor package of  claim 1 , further comprising:
 a first insulating layer on the first active surface, the first insulating surrounding the first pad; and   a second insulating layer on the second active surface, the second insulating layer surrounding the third pad,   wherein the first and second insulating layers are in contact with each other.   
     
     
         4 . The semiconductor package of  claim 1 , wherein the fourth pad is directly coupled to the second penetration via,
 wherein the second pad is vertically spaced apart from the first penetration via, and   wherein the second pad is electrically connected to the first penetration via through the sub-pad.   
     
     
         5 . The semiconductor package of  claim 1 , further comprising a test pad, which is horizontally spaced apart from the sub-pad,
 wherein a width of the test pad is greater than a width of the sub-pad.   
     
     
         6 . (canceled) 
     
     
         7 . The semiconductor package of  claim 1 , wherein a side surface of the first semiconductor chip and a side surface of the second semiconductor chip are aligned with each other in a direction perpendicular to the first active surface. 
     
     
         8 . The semiconductor package of  claim 1 , further comprising:
 a mold layer enclosing the chip structures;   a mold penetration via vertically penetrating the mold layer;   an outer connection terminal disposed on a bottom surface of the mold layer; and   a third semiconductor chip on the second inactive surface of the upper one of the chip structures,   wherein the third semiconductor chip comprises a third integrated circuit on a third active surface of a third semiconductor substrate and a fifth pad on the third active surface,   wherein a width of the fourth semiconductor chip is greater than a width each of the chip structures,   wherein the second inactive surface of the upper one of the chip structures faces the third active surface,   wherein the fourth pad of the upper one of the chip structures is directly bonded to the fifth pad, and   wherein the mold penetration via is extended from the third active surface and is connected to the outer connection terminal.   
     
     
         9 . The semiconductor package of  claim 1 , further comprising a third semiconductor chip disposed on a top surface of the chip structures and an insulating layer interposed between a top surface of the upper one of the chip structures and the third semiconductor chip,
 wherein the third semiconductor chip is attached to the top surface of the upper one of the chip structures through the insulating layer.   
     
     
         10 . A semiconductor package comprising:
 a base chip comprising:
 a base integrated circuit on a front surface of the base chip; 
 an outer connection terminal on the front surface of the base chip; and 
 a base pad on a rear surface of the base chip; and 
   chip structures vertically stacked on the base chip,   wherein each of the chip structures comprises a first semiconductor chip and a second semiconductor chip is provided on a front surface of the first semiconductor chip,   wherein the first semiconductor chip comprises:
 a first integrated circuit on a first active surface of a first semiconductor substrate; 
 a first pad on the first active surface; and 
 a pad structure on a first inactive surface of the first semiconductor substrate, 
   wherein the second semiconductor chip comprises:
 a second integrated circuit disposed on a second active surface of a second semiconductor substrate; 
 a third pad on the second active surface; and 
 a fourth pad on a second inactive surface of the second semiconductor substrate, and 
   wherein in each of the chip structures, the first pad and the third pad are in contact with each other, the rear surface of the base chip faces the first inactive surface of a lowermost one of the chip structures, and the base pad is vertically aligned with the pad structure of the lowermost one of the chip structures.   
     
     
         11 . The semiconductor package of  claim 10 , further comprising:
 a base insulating layer on the rear surface of the base chip, the base insulating layer surrounding the base pad; and   an insulating layer on the first inactive surface of the lowermost one of the chip structures, the insulating layer surrounding the pad structure,   wherein the base insulating layer and the insulating layer are in contact with each other.   
     
     
         12 . The semiconductor package of  claim 10 , wherein the first semiconductor chip further comprises a first penetration via, which penetrates through the first semiconductor substrate and is electrically connected to the first integrated circuit,
 wherein the pad structure comprises a sub-pad and a second pad,   wherein the sub-pad is disposed between the first penetration via and the second pad, and   wherein the second pad is electrically connected to the first integrated circuit through the sub-pad and the first penetration via.   
     
     
         13 . The semiconductor package of  claim 12 , further comprising a test pad on the first inactive surface, the test pad being horizontally spaced apart from the sub-pad,
 wherein the test pad and the sub-pad are comprises a same material.   
     
     
         14 . The semiconductor package of  claim 12 , wherein a distance from the first inactive surface to a bottom surface of the second pad is greater than a distance from the second inactive surface to a top surface of the fourth pad. 
     
     
         15 . The semiconductor package of  claim 10 , further comprising:
 a third semiconductor chip on a top surface of the uppermost one of the chip structures; and   an insulating layer between the top surface of the uppermost one of the chip structures and the third semiconductor chip,   wherein the third semiconductor chip is attached to the top surface of the uppermost one of the chip structures through the insulating layer.   
     
     
         16 . The semiconductor package of  claim 15 , further comprising a connection substrate on the rear surface of the base chip, the connection substrate comprising an opening,
 wherein the chip structures are disposed in the opening,   wherein a top surface of the connection substrate is coplanar with the top surface of the uppermost one of the chip structures,   wherein the third semiconductor chip is on the top surface of the connection substrate and the top surface of the uppermost one of the chip structures, and   wherein the insulating layer is extended from a region between the third semiconductor chip and the uppermost one of the chip structures to a region on the top surface of the connection substrate to fill a space between the connection substrate and the third semiconductor chip.   
     
     
         17 . The semiconductor package of  claim 16 , wherein an inner side surface of the opening is spaced apart from side surfaces of the chip structures, and
 wherein a filling layer filling a space between the inner side surface of the opening and the side surface of the chip structures.   
     
     
         18 - 23 . (canceled) 
     
     
         24 . A semiconductor package comprising:
 a first chip structure comprising a first semiconductor chip and a second semiconductor chip connected to and stacked on the first semiconductor chip; and   a second chip structure comprising a third semiconductor chip and a fourth semiconductor chip connected to and stacked on the third semiconductor chip,   wherein the second chip structure is stacked on the first chip structure such that the third semiconductor chip is connected to and stacked on the second semiconductor chip,   wherein an active surface of the first semiconductor chip with a first active device thereon faces an active surface of the second semiconductor chip with a second active device thereon, and   wherein an inactive surface of the second semiconductor chip opposite to the active surface thereof faces an inactive surface of the third semiconductor chip opposite to an active surface thereof with a third active device thereon.   
     
     
         25 . The semiconductor package of  claim 24 , wherein the active surface of the third semiconductor chip faces an active surface of the fourth semiconductor chip with a fourth active device thereon. 
     
     
         26 . The semiconductor package of  claim 24 , further comprising:
 a base chip on which the first chip structure is stacked, the base chip connected to the first chip structure; and   a molding layer or a connection substrate surrounding the first and second chip structures, on the base chip,   wherein an inactive surface of the first semiconductor chip faces the base chip.   
     
     
         27 . The semiconductor package of  claim 26 , further comprising a test pad on an inactive surface of the first semiconductor chip, the test pad not connected to the base chip.