Hard mask protection of metal interconnects

Abstract

A method for protecting metal interconnects includes depositing a first layer having a first electrochemical potential over a substrate, depositing a second layer having a second electrochemical potential over the first layer, where the second electrochemical potential is less than the first electrochemical potential. The method includes creating an opening through the second layer, and extending the opening through the first layer by etching the first layer and the second layer, where at least some of the second layer is deposited over the first layer on sidewalls of the opening.

1 . A method comprising:
 depositing a first layer having a first electrochemical potential over a substrate;   depositing a second layer having a second electrochemical potential over the first layer, wherein the second electrochemical potential is less than the first electrochemical potential;   creating an opening through the second layer; and   extending the opening through the first layer by etching the first layer and the second layer, wherein at least some of the second layer is deposited over the first layer on sidewalls of the opening during the extending.   
     
     
         2 . The method of  claim 1 , further comprising:
 removing the second layer having the opening;   exposing the sidewalls to atmosphere to oxidize the second layer deposited on the sidewalls; and   depositing a dielectric layer over the first layer to seal the opening.   
     
     
         3 . The method of  claim 2 , further comprising:
 forming a via through the dielectric layer to expose the first layer; and   filling the via with a conductor that contacts the first layer.   
     
     
         4 . The method of  claim 1 , wherein the second layer deposited over the first layer on sidewalls of the opening seals the first layer at the sidewalls. 
     
     
         5 . The method of  claim 1 , wherein etching the first layer and the second layer further comprises:
 etching using reactive ion etching.   
     
     
         6 . The method of  claim 1 , wherein:
 the first layer comprises Mo, and the second layer comprises at least one of: Ti, Ta, Nb, Co, or Ni;   the first layer comprises Ru, and the second layer comprises at least one of: Mo, Ti, Nb, Ta, W, Cu, Co, or Ni;   the first layer comprises Ir, and the second layer comprises at least one of: Mo, Ru, Ti, Nb, Ta, SiO 2 , W, Cu, Rh, Co, Pd, or Ni;   the first layer comprises Pt, and the second layer comprises at least one of: Mo, Ru, Ir, Ti, Nb, Ta, SiO 2 , W, Cu, Rh, Co, Pd, or Ni;   the first layer comprises Nb, and the second layer comprises Ti;   the first layer comprises Ta, and the second layer comprises at least one of: Ti or Nb;   the first layer comprises W, and the second layer comprises at least one of: Mo, Ti, Nb, Ta, Co, or Ni;   the first layer comprises Cu, and the second layer comprises at least one of: Mo, Ti, Nb, Ta, W, Co, or Ni;   the first layer comprises Rh, and the second layer comprises at least one of: Mo, Ru, Ti, Nb, Ta, W, Cu, Co, or Ni;   the first layer comprises Co, and the second layer comprises at least one of: Ti, Nb, or Ta;   the first layer comprises Pd, and the second layer comprises at least one of: Mo, Ru, Ti, Nb, Ta, SiO 2 , W, Cu, Rh, Co, or Ni; or   the first layer comprises Ni, and the second layer comprises at least one of: Ti, Nb, Ta, or Co.   
     
     
         7 . A process comprising:
 depositing a first metal over a semiconductor substrate comprising silicon, the first metal having a first electrochemical potential and forming a first layer;   depositing a second metal over the first layer, the second metal having a second electrochemical potential less than the first electrochemical potential and forming a second layer;   patterning the second layer to form a hard mask having an opening through the hard mask; and   etching the hard mask to extend the opening through the first layer, and, during the etching, sputtering the second metal over the first metal at sidewalls of the opening.   
     
     
         8 . The process of  claim 7 , further comprising:
 removing the second layer to expose the first layer;   oxidizing the second metal deposited on the sidewalls; and   sealing the opening by depositing a dielectric layer over the first layer.   
     
     
         9 . The process of  claim 8 , further comprising:
 forming a via through the dielectric layer to expose the first metal; and   filling the via with a third metal that contacts the first metal.   
     
     
         10 . The process of  claim 8 , wherein depositing the dielectric layer further comprises:
 depositing the dielectric layer as an airgap dielectric.   
     
     
         11 . The process of  claim 7 , wherein sputtering the second metal over the first metal at sidewalls of the opening further comprises:
 sealing the first layer from a surrounding environment at the sidewalls.   
     
     
         12 . The process of  claim 7 , wherein etching the hard mask further comprises:
 etching using reactive ion etching.   
     
     
         13 . The process of  claim 7 , wherein:
 the first layer comprises Mo, and the second layer comprises at least one of: Ti, Ta, Nb, Co, or Ni;   the first layer comprises Ru, and the second layer comprises at least one of: Mo, Ti, Nb, Ta, W, Cu, Co, or Ni;   the first layer comprises Ir, and the second layer comprises at least one of: Mo, Ru, Ti, Nb, Ta, W, Cu, Rh, Co, Pd, or Ni;   the first layer comprises Pt, and the second layer comprises at least one of: Mo, Ru, Ir, Ti, Nb, Ta, W, Cu, Rh, Co, Pd, or Ni;   the first layer comprises Nb, and the second layer comprises Ti;   the first layer comprises Ta, and the second layer comprises at least one of: Ti or Nb;   the first layer comprises W, and the second layer comprises at least one of: Mo, Ti, Nb, Ta, Co, or Ni;   the first layer comprises Cu, and the second layer comprises at least one of: Mo, Ti, Nb, Ta, W, Co, or Ni;   the first layer comprises Rh, and the second layer comprises at least one of: Mo, Ru, Ti, Nb, Ta, W, Cu, Co, or Ni;   the first layer comprises Co, and the second layer comprises at least one of: Ti, Nb, or Ta;   the first layer comprises Pd, and the second layer comprises at least one of: Mo, Ru, Ti, Nb, Ta, W, Cu, Rh, Co, or Ni; or   the first layer comprises Ni, and the second layer comprises at least one of: Ti, Nb, Ta, or Co.   
     
     
         14 . A process comprising:
 providing a plurality of layers, at least some of the layers comprising a metal mask layer, a first metal layer under the metal mask layer, and a silicon-containing layer under the first metal layer;   defining an opening in the metal mask layer;   etching the metal mask layer through the opening to define sidewalls of the metal mask layer and of the first metal layer; and   during the etching, causing a second metal from the metal mask layer to be sputtered on the sidewalls over the first metal layer, the metal mask layer having a second electrochemical potential that is less than a first electrochemical potential of the first metal layer.   
     
     
         15 . The process of  claim 14 , further comprising:
 removing the metal mask layer to expose the first metal layer;   oxidizing the second metal deposited on the sidewalls by exposing the first metal layer to oxygen; and   sealing the opening by forming a dielectric layer over the first metal layer.   
     
     
         16 . The process of  claim 15 , further comprising:
 etching a via through the dielectric layer to expose the first metal layer; and   filling the via with a third metal that contacts the first metal layer.   
     
     
         17 . The process of  claim 15 , wherein forming the dielectric layer further comprises:
 depositing the dielectric layer as an airgap dielectric.   
     
     
         18 . The process of  claim 14 , wherein causing the second metal from the metal mask layer to be sputtered on the sidewalls over the first metal layer further comprises:
 sealing the first metal layer from the environment at the sidewalls.   
     
     
         19 . The process of  claim 14 , wherein etching the metal mask layer further comprises:
 etching using reactive ion etching.   
     
     
         20 . The process of  claim 14 , wherein:
 the first metal layer comprises Mo, and the second metal comprises at least one of: Ti, Ta, Nb, Co, or Ni;   the first metal layer comprises Ru, and the second metal comprises at least one of: Mo, Ti, Nb, Ta, W, Cu, Co, or Ni;   the first metal layer comprises Ir, and the second metal comprises at least one of: Mo, Ru, Ti, Nb, Ta, W, Cu, Rh, Co, Pd, or Ni;   the first metal layer comprises Pt, and the second metal comprises at least one of: Mo, Ru, Ir, Ti, Nb, Ta, W, Cu, Rh, Co, Pd, or Ni;   the first metal layer comprises Nb, and the second metal comprises Ti;   the first metal layer comprises Ta, and the second metal comprises at least one of: Ti or Nb;   the first metal layer comprises W, and the second metal comprises at least one of: Mo, Ti, Nb, Ta, Co, or Ni;   the first metal layer comprises Cu, and the second metal comprises at least one of: Mo, Ti, Nb, Ta, W, Co, or Ni;   the first metal layer comprises Rh, and the second metal comprises at least one of: Mo, Ru, Ti, Nb, Ta, W, Cu, Co, or Ni;   the first metal layer comprises Co, and the second metal comprises at least one of: Ti, Nb, or Ta;   the first metal layer comprises Pd, and the second metal comprises at least one of: Mo, Ru, Ti, Nb, Ta, W, Cu, Rh, Co, or Ni; or   the first metal layer comprises Ni, and the second metal comprises at least one of: Ti, Nb, Ta, or Co.