method of manufacturing a new DRAM capacitor structure having increased capacitance

Abstract

A method for fabricating a stacked storage capacitor on a dynamic random access memory (DRAM) cell with increased capacitance was accomplished. The stacked capacitor is used with a field effect transistor (FET) as part of a dynamic random access memory (DRAM) cell for storing data in the form of stored charge on the capacitor. The method for making the capacitor involves forming a bottom electrode from a single polysilicon layer having a fin-shaped structure, and then using a second polysilicon layer and a plasma etch back to create a second self-aligned fin-like structure that significantly increases the surface area of the capacitor bottom electrode. The capacitor structure is then completed by forming a thin capacitor dielectric layer on the bottom electrode and depositing a third polysilicon layer to form the top electrode and complete the capacitor with significantly increased capacitance and an economy of processing steps.

What is claimed is: 
     
       1. A method for fabricating a stacked capacitor on a semiconductor substrate having a field oxide area and a device area formed thereon comprising the steps of; depositing a multilayer film comprising of a first, a second and a third insulating layer, and said second insulating layer made of a different kind of material than said first and third insulating layers;   forming an opening in said multilayer film to said device area, and thereby providing a contact opening for a bottom capacitor electrode of said stacked capacitor;   depositing conformally a first polysilicon layer on said third insulating layer and in said contact opening thereby making electrical contact to said device area;   masking and patterning said first polysilicon layer leaving portions aligned to said contact opening and extending over said third insulating layer, and thereby forming a portion of the bottom capacitor electrode of said stacked capacitor;   removing completely by isotropic etching said third insulating layer over said second insulating layer, said second insulating layer providing an etch stop layer and thereby forming from said patterned first polysilicon layer a fin-shaped bottom electrode structure for said stacked capacitor;   depositing conformally a second polysilicon layer on said patterned first polysilicon layer and on said second insulating layer;   etching anisotropically said second polysilicon layer, leaving portions of said second polysilicon layer under and on sides of said fin-shaped bottom electrode structure, and on said second insulating layer, thereby forming said bottom capacitor electrode;   depositing conformally a capacitor dielectric layer over said bottom capacitor electrode and on said second insulating layer; and   depositing a conformal third polysilicon layer over said capacitor dielectric layer;   patterning said third polysilicon layer thereby forming a top capacitor electrode of said stacked capacitor.   
     
     
       2. The method of claim 1, wherein said first and third insulating layers are composed of silicon oxide (SiO 2 ) deposited by chemical vapor deposition (CVD). 
     
     
       3. The method of claim 2, wherein the thickness of said first insulating layer is between about 800 to 4000 Angstroms. 
     
     
       4. The method of claim 2, wherein the thickness of said third insulating layer is between about 2000 to 5000 Angstroms. 
     
     
       5. The method of claim 1, wherein said second insulating layer is composed of silicon nitride (Si 3  N 4 ) deposited by chemical vapor deposition. 
     
     
       6. The method of claim 5, wherein the thickness of said silicon nitride layer is between about 100 to 500 Angstroms. 
     
     
       7. The method of claim 1, wherein said first polysilicon layer is deposited by chemical vapor deposition (CVD) having a thickness of between about 1000 to 5000 Angstroms. 
     
     
       8. The method of claim 7, wherein said first polysilicon layer is doped with N type impurities having a concentration of between about 5 E 19 to 1 E 21 atoms/cm 3 . 
     
     
       9. The method of claim 1, wherein said third insulating layer is isotropically etched in an aqueous solution of hydrofluoric acid (HF). 
     
     
       10. The method of claim 1, wherein said second polysilicon layer is deposited by chemical vapor deposition (CVD) having a thickness of between about 500 to 1500 Angstroms. 
     
     
       11. The method of claim 10, wherein said second polysilicon layer is doped with N type impurities having a concentration of between about 5 E 19 to 1 E 21 atoms/cm 3 . 
     
     
       12. The method of claim 1, wherein said capacitor dielectric layer is silicon oxide/silicon nitride/silicon oxide. 
     
     
       13. The method of claim 12, wherein the thickness of said capacitor dielectric layer is between about 50 to 200 Angstroms. 
     
     
       14. The method of claim 1, wherein the thickness of said third polysilicon layer is between about 1000 to 3000 Angstroms. 
     
     
       15. A method for fabricating a dynamic random access memory (DRAM) device having an array of stacked capacitors, comprising the steps of: providing a semiconductor substrate having field oxide areas surrounding and isolating device areas, said device areas having formed therein field effect transistors (FETs) with source/drain regions; and   further comprising the steps of making said stacked capacitors by;   depositing a multi-layer film comprising of a first, a second and a third insulating layer, and said second insulating layer made of a different kind of material than said first and third insulating layers;   forming openings in said multi-layer film to one of said source/drain regions of each of said FETs, and thereby providing contact openings for bottom capacitor electrodes of said stacked capacitors;   depositing conformally a first polysilicon layer on said third insulating layer and in said contact openings, and thereby making electrical contact to said one of said source/drain regions;   masking and patterning said first polysilicon layer leaving portions aligned to said contact openings and extending over said third insulating layer, and thereby forming a portion of the bottom capacitor electrodes of said stacked capacitors;   removing completely by isotropic etching said third insulating layer over said second insulating layer, said second insulating layer providing an etch stop layer and thereby forming from said patterned first polysilicon layer fin-shaped bottom electrode structures for said stacked capacitors;   depositing conformally a second polysilicon layer on said patterned first polysilicon layer and on said second insulating layer;   etching anisotropically said second polysilicon layer, leaving portions of said second polysilicon layer under and on sides of said fin-shaped bottom electrode structures, and on said second insulating layer, thereby forming said bottom capacitor electrodes;   depositing conformally a capacitor dielectric layer over said bottom capacitor electrodes and on said second insulating layer; and   depositing a conformal third polysilicon layer over said capacitor dielectric layer;   patterning said third polysilicon layer thereby forming top capacitor electrodes of said dynamic random access memory (DRAM) device having an array of stacked capacitors.   
     
     
       16. The method of claim 15, wherein said first and third insulating layers are composed of silicon oxide (SiO 2 ) deposited by chemical vapor deposition (CVD). 
     
     
       17. The method of claim 16, wherein the thickness of said first insulating layer is between about 800 to 4000 Angstroms. 
     
     
       18. The method of claim 16, wherein the thickness of said third insulating layer is between about 2000 to 5000 Angstroms. 
     
     
       19. The method of claim 15, wherein said second insulating layer is composed of silicon nitride (Si 3  N 4 ) deposited by chemical vapor deposition. 
     
     
       20. The method of claim 19, wherein the thickness of said silicon nitride layer is between about 100 to 500 Angstroms. 
     
     
       21. The method of claim 15, wherein said first polysilicon layer is deposited by chemical vapor deposition (CVD) having a thickness of between about 1000 to 5000 Angstroms. 
     
     
       22. The method of claim 21, wherein said first polysilicon layer is doped with N type impurities having a concentration of between about 5 E 19 to 1 E 21 atoms/cm 3 . 
     
     
       23. The method of claim 15, wherein said third insulating layer is isotropically etched in an aqueous solution of hydrofluoric acid (HF). 
     
     
       24. The method of claim 15, wherein said second polysilicon layer is deposited by chemical vapor deposition (CVD) having a thickness of between about 500 to 1500 Angstroms. 
     
     
       25. The method of claim 24, wherein said second polysilicon layer is doped with N type impurities having a concentration of between about 5 E 19 to 1 E 21 atoms/cm 3 . 
     
     
       26. The method of claim 15, wherein said capacitor dielectric layer is silicon oxide/silicon nitride/silicon oxide. 
     
     
       27. The method of claim 26, wherein the thickness of said capacitor dielectric layer is between about 50 to 200 Angstroms. 
     
     
       28. The method of claim 15, wherein the thickness of said third polysilicon layer is between about 1000 to 3000 Angstroms.