Salicide integration method

Abstract

A method for preventing gate to source/drain bridging and reducing junction leakage by preventing defects in the source/drain region in the fabrication of a silicided polysilicon gate is described. A polysilicon gate electrode on a semiconductor substrate and associated source and drain regions within the semiconductor substrate are provided wherein spacers are formed on the sidewalls of the gate electrode. A layer of titanium is deposited over the gate electrode, spacers and source and drain regions within the semiconductor substrate. Arsenic ions are implanted into the titanium layer. The semiconductor substrate is annealed for a first time whereby the titanium layer is transformed into a titanium silicide layer except where the titanium layer overlies the spacers. The titanium layer overlying the spacers is stripped to leave the titanium silicide layer only on the top surface of the gate electrode and on the top surface of the semiconductor substrate overlying the source and drain regions. The semiconductor substrate is annealed for a second time whereby the titanium silicide is transformed into a lower resistance phase. An insulating layer is deposited over the surface of the semiconductor substrate covering the gate electrode. Metallization with electrical connections is provided to complete the fabrication of the integrated circuit device.

What is claimed is: 
     
       1. A method of fabricating an integrated circuit device comprising: providing a polysilicon gate electrode on a semiconductor substrate and associated source and drain regions within said semiconductor substrate wherein spacers are formed on the sidewalls of said gate electrode;   conformally depositing a layer of titanium over said gate electrode, said spacers and said source and drain regions within said semiconductor substrate;   implanting arsenic ions into said titanium layer;   first annealing said semiconductor substrate whereby said titanium layer is transformed into a titanium silicide layer except where said titanium layer overlies said spacers and whereby said arsenic ions stuff the grain boundaries of said titanium silicide layer thereby preventing diffusion of silicon from said titanium silicide layer into said titanium layer overlying said spacers;   stripping said titanium layer overlying said spacers to leave said titanium silicide layer only on the top surface of said gate electrode and on the top surface of said semiconductor substrate overlying said source and drain regions;   second annealing said semiconductor substrate whereby the resistance of said titanium silicide layer is decreased;   depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode; and   providing metallization with electrical connections to complete the fabrication of said integrated circuit device.   
     
     
       2. The method according to claim 1 wherein said spacers comprise silicon nitride and have a width of between about 800 and 1500 Angstroms. 
     
     
       3. The method according to claim 1 wherein said spacers comprise silicon oxide and have a width of between about 800 and 1500 Angstroms. 
     
     
       4. The method according to claim 1 wherein said titanium layer is deposited to a thickness of between about 250 and 400 Angstroms. 
     
     
       5. The method according to claim 1 wherein said arsenic ions are implanted at a dosage of between about 4×10 14  and 8×10 14  atoms/cm 2  and an energy of between about 20 and 40 KeV. 
     
     
       6. The method according to claim 1 wherein said first annealing is a rapid thermal anneal (RTA) performed in a nitrogen ambient at a temperature of between about 725° and 740° C. for between about 20 to 30 seconds. 
     
     
       7. The method according to claim 1 wherein said stripping of said titanium layer overlying said spacers is done using NH 4  OH/H 2  O 2  /H 2  O. 
     
     
       8. The method according to claim 1 wherein said second annealing is a rapid thermal anneal (RTA) performed in a nitrogen ambient at a temperature of between about 840° to 900° C. for between about 10 to 30 seconds. 
     
     
       9. A method of fabricating an integrated circuit device comprising: growing a layer of gate silicon oxide over the surface of a semiconductor substrate;   depositing a polysilicon layer overlying said gate silicon oxide layer;   etching away said polysilicon and said gate oxide layers where they are not covered by a mask to form a gate electrode;   implanting first BF 2  ions to form lightly doped regions within said semiconductor substrate using said gate electrode as a mask;   depositing a dielectric layer overlying said semiconductor substrate and said gate electrode; anisotropically etching said dielectric layer to leave spacers on the sidewalls of said gate electrode;   implanting second BF 2  ions to form P+ source and drain regions within said semiconductor substrate using said gate electrode and said spacers as a mask;   conformally depositing a layer of titanium over the surfaces of said semiconductor substrate;   implanting arsenic ions into said titanium layer;   first annealing said semiconductor substrate whereby said titanium layer is transformed into a titanium silicide layer except where said titanium layer overlies said spacers and whereby said arsenic ions stuff the grain boundaries of said titanium silicide layer thereby preventing diffusion of silicon from said titanium silicide layer into said titanium layer overlying said spacers;   stripping said titanium layer overlying said spacers to leave said titanium silicide layer only on the top surface of said gate electrode and on the top surface of said semiconductor substrate overlying said source and drain regions;   second annealing said semiconductor substrate whereby said titanium silicide layer has lower resistance;   depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode; and   providing metallization with electrical connections to complete the fabrication of said integrated circuit device.   
     
     
       10. The method according to claim 9 wherein said polysilicon layer is deposited by low pressure chemical vapor deposition to a thickness of between about 2000 and 3000 Angstroms. 
     
     
       11. The method according to claim 9 wherein said dielectric layer is deposited to a thickness of between about 1000 and 1500 Angstroms. 
     
     
       12. The method according to claim 9 wherein said dielectric layer comprises silicon nitride. 
     
     
       13. The method according to claim 9 wherein said dielectric layer comprises silicon oxide. 
     
     
       14. The method according to claim 9 wherein said spacers have a width of between about 800 and 1500 Angstroms. 
     
     
       15. The method according to claim 9 wherein said titanium layer is deposited to a thickness of between about 250 and 400 Angstroms. 
     
     
       16. The method according to claim 9 wherein said arsenic ions are implanted at a dosage of between about 4×10 14  and 8×10 14  atoms/cm 2  and an energy of between about 20 and 40 KeV. 
     
     
       17. The method according to claim 9 wherein said first annealing is a rapid thermal anneal (RTA) performed in a nitrogen ambient at a temperature of between about 725° and 740° C. for between about 20 to 30 seconds. 
     
     
       18. The method according to claim 9 wherein said second annealing is a rapid thermal anneal (RTA) performed in a nitrogen ambient at a temperature of between about 840° to 900° C. for between about 10 to 30 seconds. 
     
     
       19. A method of fabricating an integrated circuit device comprising: providing a polysilicon gate electrode on a semiconductor substrate and associated source and drain regions within said semiconductor substrate wherein spacers are formed on the sidewalls of said gate electrode;   conformally depositing a layer of titanium over said gate electrode, said spacers and said source and drain regions within said semiconductor substrate;   implanting arsenic ions into said titanium layer;   first annealing said semiconductor substrate whereby said titanium layer overlying said gate electrode and said semiconductor substrate is transformed into a titanium silicide layer and wherein said arsenic ions within said titanium layer stuff the grain boundaries of said titanium layer whereby titanium silicon does not form overlying said spacers and whereby said arsenic ions stuff the grain boundaries of said titanium silicide layer thereby preventing diffusion of silicon from said titanium silicide layer into said titanium layer overlying said spacers;   stripping said titanium layer overlying said spacers;   second annealing said semiconductor substrate whereby the resistance of said titanium silicide layer is decreased;   depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode; and   providing metallization with electrical connections to complete the fabrication of said integrated circuit device.   
     
     
       20. The method according to claim 19 wherein said spacers comprise one of the group containing silicon oxide and silicon nitride and wherein said spacers have a width of between about 800 and 1500 Angstroms. 
     
     
       21. The method according to claim 19 wherein said titanium layer is deposited to a thickness of between about 250 and 400 Angstroms. 
     
     
       22. The method according to claim 19 wherein said arsenic ions are implanted at a dosage of between about 4×10 14  and 8×10 14  atoms/cm 2  and an energy of between about 20 and 40 KeV.