Three dimensional polysilicon resistor for integrated circuits

Abstract

A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the insulating layer. A polysilicon layer is formed upon the insulating layer and formed conformally into the aperture(s) within the insulating layer. The polysilicon layer is then patterned to form a resistor which includes the portion of the polysilicon layer which resides within the aperture(s).

What is claimed is: 
     
       1. A method for forming a polysilicon resistor for use in integrated circuits comprising: providing a semiconductor substrate;   forming over the semiconductor substrate a conductor layer;   forming over the conductor layer an insulating layer, the insulating layer having an aperture formed partially through the insulating layer, the aperture being bounded by insulating layer, the insulating layer also having a via formed through the insulating layer, the via accessing the conductor layer;   forming upon the insulating layer a polysilicon layer, the polysilicon layer being formed conformally into the aperture and conformally into the via without filling the aperture; and   patterning the polysilicon layer to form a polysilicon resistor and a pair of polysilicon electrode ends contiguous with the polysilicon resistor, where the polysilicon resistor includes a portion of the polysilicon layer formed conformally into the aperture within the insulating layer and where a polysilicon electrode end within the pair of polysilicon electrode ends includes a portion of the polysilicon layer(s) formed conformally into the via and contacting the conductor layer.   
     
     
       2. The method of claim 1 wherein the insulating layer is formed from silicon oxide. 
     
     
       3. The method of claim 2 wherein the thickness of the insulating layer is about 4000 to about 15000 angstroms. 
     
     
       4. The method of claim 1 wherein the depth of the aperture(s) into which is formed the polysilicon layer is about 4000 to about 16000 angstroms. 
     
     
       5. The method of claim 1 wherein the minimum cross-sectional dimension of the aperture(s) into which is formed the polysilicon layer is about 6000 angstroms. 
     
     
       6. The method of claim 1 wherein the thickness of the polysilicon layer is about 300 to about 1000 angstroms. 
     
     
       7. The method of claim 6 wherein the polysilicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) process employing silane as the silicon source material. 
     
     
       8. The method of claim 1 wherein each polysilicon electrode end within the pair of polysilicon electrode ends is formed through ion implanting the polysilicon electrode end with a dopant ion chosen from the group of dopant ions consisting of arsenic dopant ion, phosphorus dopant ion and boron dopant ion. 
     
     
       9. The method of claim 8 it wherein the dopant ion is phosphorus dopant ion. 
     
     
       10. The method of claim 9 where the phosphorus dopant ion is implanted at about 1E14 to about 1E16 ions per square centimeter ion implantation dose and about 25 to about 40 keV ion implantation energy. 
     
     
       11. A polysilicon resistor for use in integrated circuits comprising: a semiconductor substrate;   a conductor layer formed over the semiconductor substrate;   an insulating layer formed over the conductor layer, the insulating layer having an aperture formed partially through the insulating layer, where the aperture is bounded by the insulating layer the insulating layer also having formed therethrough a via accessing the conductor layer; and   a patterned polysilicon layer formed upon the insulating layer, the patterned polysilicon layer being formed conformally into the aperture and conformally into the via without filling the aperture, the patterned polysilicon layer forming a polysilicon resistor and a pair of polysilicon electrode ends contiguous with the polysilicon resistor, where the polysilicon resistor includes a portion of the polysilicon layer formed conformally into the aperture within the insulating layer and where a polysilicon electrode end within the pair of polysilicon electrode ends includes a portion of the polysilicon layer formed within the via and contacting the conductor layer.   
     
     
       12. The polysilicon resistor of claim 11 wherein the insulating layer is formed from a silicon oxide and the insulating layer is about 4000 to about 15000 angstroms thick. 
     
     
       13. The polysilicon resistor of claim 11 wherein the depth of the aperture(s) into which the polysilicon layer is formed is about 4000 to about 16000 angstroms in depth and the minimum cross-sectional dimension of the aperture(s) into which the polysilicon layer is formed is about 6000 angstroms. 
     
     
       14. The polysilicon resistor of claim 11 wherein the polysilicon layer is about 300 to about 1000 angstroms thick. 
     
     
       15. The polysilicon resistor of claim 11 wherein each polysilicon electrode end within the pair of polysilicon electrode ends is implanted with phosphorus dopant ions at about 1E14 to about 1E16 ions per square centimeter dose and about 25 to about 40 keV ion implantation energy.