Method for manufacturing mixed-mode devices

Abstract

A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing operation. This method uses the same chemical processing conditions for etching the oxide layer and the removal of photoresist layer, so that no watermarks remain after the etching and cleaning processes. MOS transistors are formed over the thin gate oxide layer region and the thick gate oxide region are of, two types, each having a different gate oxide layer thickness so that each has a different operating voltage.

What is claimed is: 
     
       1. A method for manufacturing mixed-mode devices comprising the steps of: providing a substrate having a plurality of shallow trench isolation structures formed thereon;   forming a first gate oxide layer over the substrate and the shallow trench isolation structures;   forming a photoresist layer over the first gate oxide layer, then using a photolithographic process to pattern the photoresist layer into a plurality of patches covering thick gate oxide layer regions;   etching away a portion of the first gate oxide layer using a wet etching solution;   immersing the substrate, the first gate oxide layer and the shallow trench isolation structures in water to rinse away the wet etching solution;   removing the photoresist layer using an acid solution, wherein the steps of etching the first gate oxide layer, immersing the substrate, and removing the photoresist layer are all performed in same wet chemical processing environment;   forming a second gate oxide layer over the first gate oxide layer and the substrate, creating a plurality of thin gate oxide layer regions covered only by the second gate oxide layer and a plurality of thick gate oxide layer regions covered by the first gate oxide layer and the second gate oxide layer together; and   forming a plurality of transistor structures above the thin gate oxide layer region and the thick gate oxide region.   
     
     
       2. The method of claim 1, after removing the photoresist layer further comprising performing a cleaning step, wherein the cleaning step and the step of etching the first gate oxide layer are performed in the same wet chemical processing environment. 
     
     
       3. The method of claim 2, wherein the step of etching the first gate oxide layer and the removal of the photoresist layer includes using a buffered oxide etchant for said etching, water for removing residual buffered oxide etchant, and sulfuric acid (H 2  SO 4 ) solution for said removal. 
     
     
       4. The method of claim 3, wherein after the step of etching the first gate oxide layer and the removal of the photoresist layer, further includes a drying operation to remove the residual sulfuric acid solution on the substrate. 
     
     
       5. The method of claim 4, wherein after the step of drying the substrate includes a spin-drying method. 
     
     
       6. The method of claim 4, wherein after the step of drying the substrate includes a solution drying method. 
     
     
       7. The method of claim 6, wherein after the step of drying the substrate includes using an isopropyl alcohol. 
     
     
       8. The method of claim 1, wherein the step of forming the transistor structures includes the steps of: forming a plurality of gate structures above the thin gate oxide layer region and the thick gate oxide region; and   forming a plurality of source and drain regions in the substrate on each side of the gate structures.   
     
     
       9. The method of claim 8, wherein the step of forming the gate structures includes depositing doped polysilicon. 
     
     
       10. The method of claim 8, wherein the step of forming the source and drain regions includes using the gate structures as a mask to carry out a dopants implant operation. 
     
     
       11. A method for manufacturing mixed-mode devices comprising the steps of: providing a substrate having a plurality of shallow trench isolation structures formed thereon;   forming a first gate oxide layer over the substrate and the shallow trench isolation structures;   forming a photoresist layer over the first gate oxide layer, then using a photolithographic process to pattern the photoresist layer into a plurality of patches covering thick gate oxide layer regions;   etching away a portion of the first gate oxide layer using a buffered oxide etchant;   immersing the substrate, the first gate oxide layer and the shallow trench isolation structures in water to rinse away the wet buffered oxide etchant;   removing the photoresist layer using a sulfuric acid solution;   cleaning the substrate using a cleaning solution, wherein the above steps of etching the first gate oxide layer, immersing the substrate, removing the photoresist layer and cleaning the substrate are all performed in same wet chemical processing environment and performed in the above order;   forming a second gate oxide layer over the first gate oxide layer and the substrate, creating a plurality of thin gate oxide layer regions covered only by the second gate oxide layer and a plurality of thick gate oxide layer regions covered by the first gate oxide layer and the second gate oxide layer together; and   forming a plurality of transistor structures above the thin gate oxide layer region and the thick gate oxide region.