P
US6465337B1ExpiredUtilityPatentIndex 92

Methods of fabricating integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Jun 24, 1998Filed: Sep 18, 2000Granted: Oct 15, 2002
Est. expiryJun 24, 2018(expired)· nominal 20-yr term from priority
Inventors:LEE SOO CHEOLAHN JONG-HYONLEE HYAE-RYOUNG
H10W 72/9232H10W 72/5449H10W 72/983H10W 72/952H10W 72/951H10W 72/932H10W 72/923H10W 72/536H10W 72/251H10W 72/075H10W 72/59H10W 72/29H10W 72/012
92
PatentIndex Score
18
Cited by
20
References
5
Claims

Abstract

Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart conductive layers and an array of spaced apart insulating islands in the third continuous conductive layer that extend therethrough such that sidewalls of the insulating islands are surrounded by the third continuous conductive layer. A fourth continuous conductive layer also may be provided between the third continuous conductive layer and the second conductive layer and a second array of spaced apart insulating islands may be provided in the fourth continuous conductive layer, that extend therethrough, such that sidewalls of the insulating islands are surrounded by the fourth continuous conductive layer. A fifth continuous conductive layer also may be provided between the third and fourth continuous conductive layers and a third array of spaced apart insulating islands may be provided in the fifth continuous conductive layer, that extend therethrough, such that sidewalls of the third array of insulating islands are surrounded by the fifth continuous conductive layer. The first and second arrays of spaced apart insulating islands preferably laterally overlap each other and may be congruent to each other. The third array of spaced apart insulating islands also may laterally overlap the first and second arrays. Preferably, the third array of spaced apart insulating islands are of the same shape as the first array, but of different sizes.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A method of fabricating an internal structure of a bonding pad for an integrated circuit comprising the steps of: 
       forming an underlying conductive layer on an integrated circuit substrate;  
       forming a continuous conductive layer on the underlying conductive layer and electrically connected thereto, the continuous conductive layer including therein an array of spaced apart insulating islands that extend therethrough such that sidewalls of the insulating islands are surrounded by the continuous conductive layer; and  
       forming an overlying conductive layer on the continuous conductive layer and electrically connected thereto.  
     
     
       2. A method according to  claim 1  wherein the step of forming a continuous conductive layer comprises the steps of: 
       forming a solid conductive layer on the underlying conductive layer, electrically connected thereto;  
       etching a plurality of spaced apart vias in the solid conductive layer that extend therethrough;  
       forming an insulating layer on the solid conductive layer and in the vias; and  
       removing the insulating layer from on the solid conductive layer such that the insulating layer remains in the vias.  
     
     
       3. A method according to  claim 1  wherein the step of forming a continuous conductive layer comprises the steps of: 
       forming a solid insulating layer on the underlying conductive layer;  
       etching the solid insulating layer to define a plurality of spaced apart insulating islands on the underlying conductive layer;  
       forming an intermediate conductive layer on the underlying conductive layer between the islands and on the islands; and  
       removing the intermediate conductive layer from on the islands such that the intermediate conductive layer remains between the islands.  
     
     
       4. A method according to  claim 1  wherein the step of forming a continuous conductive layer is repeatedly performed prior to the step of forming an overlying conductive layer. 
     
     
       5. A method according to  claim 1  wherein the steps of forming a continuous conductive layer and forming an overlying layer are repeatedly and sequentially performed.

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