Memory cell with nanocrystals or nanodots

Abstract

The storage layer ( 6 ) is in each case present above a region in which the channel region ( 3 ) adjoins a source/drain region ( 2 ) and is in each case interrupted above an intervening middle part of the channel region ( 3 ). The storage layer ( 6 ) is formed by material of the gate dielectric ( 4 ) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode ( 5 ) is widened at the flanks by electrically conductive spacers ( 7 ).

1. A memory cell comprising;
 first and second source/drain regions disposed at a top side of a semiconductor body through the introduction of dopant, 
 a channel region provided between the first and second source/drain regions; 
 a gate dielectric and a gate electrode arranged on the channel region, said gate electrode defining a source-side flank and a drain-side flank and arranged in a word line web comprising at least two word line layers; 
 electrically conductive spacers arranged on said source-side flank and said drain-side flank of said gate electrode and electrically connected thereto, said electrically conductive spacers are arranged at the flanks of a first word line layer, further arranged at the bottom of the word line web and having at least one second word line layer projecting over said electrically conductive spacers; and 
 a storage layer disposed above the transition or boundary between a channel region and at least one of the source/drain regions, the storage layer being interrupted above an intervening, central part of the channel region and, the storage layer being formed as a portion of the gate dielectric and containing nanocrystals or nanodots. 
 
   
   
     2. The memory cell as claimed in  claim 1 , wherein the storage layer is formed as a single layer from a base material of the same type as the gate dielectric, and the material of the nanocrystals or nanodots have been introduced through ion implantation. 
   
   
     3. The memory cell as claimed in  claim 1 , wherein the material of the nanocrystals or nanodots is selected to form bonding locations for charge carriers. 
   
   
     4. The memory cell as claimed in  claim 1 , wherein the material of the nanocrystals or nanodots comprises at least one material selected from the group consisting of silicon oxynitride, indium, gallium, tin, arsenic and tungsten. 
   
   
     5. The memory cell as claimed in  claim 1 , wherein the electrical connection between the electrically conductive spacers and the gate electrode is formed in part by at least one of the source-side and/or the drain-side flank of the gate electrode. 
   
   
     6. The memory cell as claimed in  claim 1 , wherein the electrically conductive spacers comprise polysilicon. 
   
   
     7. The memory cell as claimed in  claim 1 , wherein the semiconductor body comprises a semiconductor substrate.