SONOS memory device having nano-sized trap elements

Abstract

A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

1. A silicon-oxide-nitride-oxide-silicon (SONOS) memory device including a memory type transistor in which a gate is formed with a SONOS structure on a semiconductor substrate, wherein the gate comprises:
 a tunneling oxide layer; 
 a memory node structure formed on the tunneling oxide layer and having a trap site in which charges passing through the tunneling oxide layer are trapped, the memory node structure including crystal layers having nanocrystals that are separated from one another to trap the charges; and 
 a gate electrode formed on the memory node structure, wherein the memory node structure comprises: 
 a first memory node layer, including a first crystal layer and a first insulating layer, the first crystal layer being isolated from the second memory node layer; 
 a second memory node layer, including a dielectric layer having a trap site with a predetermined density; and 
 a third memory node layer, including a second crystal layer and a second insulating layer, the second crystal layer being isolated from the second memory node layer and the gate electrode. 
 
     
     
       2. The SONOS memory device as claimed in  claim 1 , wherein the dielectric layer is a nitride layer. 
     
     
       3. A silicon-oxide-nitride-oxide-silicon (SONOS) memory device including a memory type transistor in which a gate is formed with a SONOS structure on a semiconductor substrate, wherein the gate comprises:
 a tunneling oxide layer; 
 a memory node structure formed on the tunneling oxide layer and having a trap site in which charges passing through the tunneling oxide layer are trapped, wherein the memory node structure includes nano-sized trap elements in which the charges are trapped; and 
 a gate electrode formed on the memory node structure, wherein the memory node structure comprises: 
 a first memory node layer, including a first nano-sized trap element and a first insulating layer, the first nano-sized trap element being isolated from the second memory node layer; 
 a second memory node layer, including a dielectric layer having a trap site with a predetermined density; and 
 a third memory node layer, including a second nano-sized trap element and a second insulating layer, the second nano-sized trap element being isolated from the second memory node layer and the gate electrode. 
 
     
     
       4. The SONOS memory device as claimed in  claim 3 , wherein the nano-sized trap element is a crystal layer composed of nanocrystals that are separated from one another. 
     
     
       5. The SONOS memory device as claimed in  claim 3 , wherein each of the first nano-sized trap element and the second nano-sized trap element is a crystal layer composed of nanocrystals that are separated from one another.