Semiconductor assemblies including redistribution layers and packages and assemblies formed therefrom

Abstract

Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages created by the methods, are disclosed. A sacrificial layer is deposited on a support substrate. An etch stop layer having a lower etch is deposited on the sacrificial layer. Redistribution lines in a dielectric material are formed on the support substrate on the etch stop layer. Semiconductor dice, either singulated or at the wafer level, are connected to the redistribution lines. The assembly may be scribed to allow the sacrificial layer to be etched to enable removal of the semiconductor dice and associated redistribution layer from the support substrate. The etch stop layer is removed to allow access to the redistribution lines for conductive bumping.

1. An intermediate wafer level assembly for fabrication of semiconductor component packages, the intermediate wafer level assembly comprising:
 a support substrate; 
 a layer of sacrificial material disposed on the support substrate; 
 an etch stop layer of material disposed directly on the layer of sacrificial material; 
 at least one level of conductive redistribution lines disposed in a dielectric material on the etch stop layer; and 
 a plurality of semiconductor dice disposed on the at least one level of conductive redistribution lines and mechanically and electrically connected thereto. 
 
     
     
       2. The intermediate wafer level assembly of  claim 1 , wherein each of the plurality of semiconductor dice is mechanically and electrically connected to lines of the at least one level of conductive redistribution lines by discrete conductive elements carried on active surfaces of the plurality of semiconductor dice. 
     
     
       3. The intermediate wafer level assembly of  claim 2 , wherein the discrete conductive elements comprise solder balls, other metal or alloy balls, metal coated polymer balls, bumps or studs, or bumps or pillars of conductive or conductor-filled epoxy. 
     
     
       4. The intermediate wafer level assembly of  claim 2 , further comprising a dielectric underfill disposed between the semiconductor dice of the plurality of semiconductor dice and the at least one level of conductive redistribution lines and surrounding the discrete conductive elements. 
     
     
       5. The intermediate wafer level assembly of  claim 1 , wherein the plurality of semiconductor dice comprises known good dice. 
     
     
       6. The intermediate wafer level assembly of  claim 1 , wherein the layer of sacrificial material comprises a silicon oxide, aluminum borophosphosilicate glass (BPSG) or TEOS. 
     
     
       7. The intermediate wafer level assembly of  claim 1 , wherein the etch stop layer comprises TEOS or a polymeric material. 
     
     
       8. The intermediate wafer level assembly of  claim 1 , wherein the etch stop layer comprises material exhibiting a significantly lower etch rate to a selected etchant than the layer of sacrificial material. 
     
     
       9. The intermediate wafer level assembly of  claim 1 , wherein the at least one level of conductive redistribution lines comprises at least one of copper, nickel, gold, aluminum and alloys thereof. 
     
     
       10. The intermediate wafer level assembly of  claim 1 , wherein the dielectric material comprises at least one of BCB, a polyimide, TEOS, silicon nitride, a photosensitive dielectric, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG). 
     
     
       11. The intermediate wafer level assembly of  claim 1 , wherein the support substrate comprises a semiconductor material, BT resin, an FR-4 laminate, an FR-5 laminate, a ceramic, a metal material, or a polymeric material. 
     
     
       12. The intermediate wafer level assembly of  claim 1 , wherein the plurality of semiconductor dice comprises singulated dice, and further comprising an encapsulant disposed over sides and back sides of the semiconductor dice of the plurality of semiconductor dice. 
     
     
       13. The intermediate wafer level assembly of  claim 1 , wherein the plurality of semiconductor dice comprises unsingulated semiconductor dice on a semiconductor wafer. 
     
     
       14. The intermediate wafer level assembly of  claim 1 , wherein each of the plurality of semiconductor dice is of less than about 10 μm thickness. 
     
     
       15. A semiconductor component package, comprising:
 at least one semiconductor die having a plurality of discrete conductive elements protruding from an active surface thereof; 
 the plurality of discrete conductive elements being mechanically and electrically connected to a plurality of terminal pads, the plurality of terminal pads being mechanically and electrically connected to at least one level of conductive redistribution lines disposed within a dielectric material and wherein each of the plurality of terminal pads extends from the at least one level of conductive redistribution lines through an aperture in the dielectric material to an upper surface of the dielectric material and is positioned to receive at least one of the plurality of the discrete conductive elements; and 
 another plurality of discrete conductive elements mechanically and electrically connected to the at least one level of conductive redistribution lines and protruding from the dielectric material on an opposing side thereof from the at least one semiconductor die. 
 
     
     
       16. The semiconductor component package of  claim 15 , further including a dielectric underfill material disposed between the at least one semiconductor die and the dielectric material. 
     
     
       17. The semiconductor component package of  claim 15 , wherein sides and a back side of the at least one semiconductor die are encapsulated with a dielectric material. 
     
     
       18. The semiconductor component package of  claim 15 , wherein the at least one semiconductor die comprises a plurality of semiconductor dice. 
     
     
       19. The semiconductor component package of  claim 18 , wherein each of the plurality of semiconductor dice is electrically connected through the at least one level of redistribution lines. 
     
     
       20. The semiconductor component package of  claim 15 , wherein the at least one semiconductor die is a known good die. 
     
     
       21. The semiconductor component package of  claim 15 , wherein the at least one semiconductor die is of less than about 10 μm thickness.