Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffraction

Abstract

By providing test features of increased thickness in a test structure for performing an x-ray diffraction measurement for evaluating the crystalline characteristics, such as the contents of germanium, an increased accuracy may be achieved, since the patterned SOI layer may be used as an efficient reference for the required data analysis.

1. A method, comprising:
 providing a substrate comprising a silicon-on-insulator (SOI) portion having a crystalline base layer, a buried insulator layer, and a crystalline semiconductor layer; 
 forming a test structure on said substrate, said test structure including a semiconductor alloy embedded in said crystalline semiconductor layer; 
 increasing a signal/noise ratio of a response to a probing x-ray diffractometry beam by at least one of adjusting a ratio of material of said crystalline semiconductor layer and said semiconductor alloy in said test structure or increasing a lattice mismatch of said crystalline base layer in said crystalline semiconductor layer; and 
 determining at least one characteristic of said semiconductor alloy using said crystalline semiconductor layer within said test structure as a reference. 
 
     
     
       2. The method of  claim 1 , wherein said signal/noise ratio is increased by adjusting a ratio of material of said crystalline semiconductor layer and said semiconductor alloy in said test structure by providing a plurality of regions of said semiconductor alloy. 
     
     
       3. The method of  claim 2 , wherein said plurality of regions is provided to have at least one lateral device dimension that corresponds to a design dimension of a transistor element. 
     
     
       4. The method of  claim 3 , wherein providing said plurality of regions comprises forming said plurality of regions in said test structure and forming a plurality of transistor elements in a common manufacturing process. 
     
     
       5. The method of  claim 1 , further comprising forming said SOI portion by a substrate bond process and adjusting a lattice mismatch between a first substrate comprising said crystalline base layer and a second substrate comprising said crystalline semiconductor layer. 
     
     
       6. The method of  claim 1 , wherein forming said semiconductor alloy comprises performing an epitaxial growth process. 
     
     
       7. The method of  claim 1 , wherein forming said semiconductor alloy comprises performing an implantation process.