Nonvolatile single-poly memory device

Abstract

A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.

1. A non-volatile single-poly memory cell for one bit storage, comprising:
 a first unit cell comprising a select gate, a first P +  source doped region and a first P +  drain/source doped region, wherein the select gate, the first P +  source doped region and the first P +  drain/source doped region constitute a first select transistor; the first unit cell further comprising: a first floating gate transistor series connecting with the first select transistor in a first row, and the first floating gate transistor comprising a first floating gate, the first P +  drain/source doped region and a first P +  drain doped region, wherein the first select transistor uses the first P +  drain/source doped region mutually with the first floating gate transistor; and 
 a second unit cell parallel connected to the first unit cell, the second unit cell comprising a second select transistor consisting of the select gate extending from the first unit cell, a second P +  source doped region and a second P +  drain/source doped region; the second unit cell further comprising a second floating gate transistor series connecting with the second select transistor in a second row, and the second floating gate transistor comprising a second floating gate arranged in the same column as the first floating gate, the second P +  drain/source doped region and a second P +  drain doped region, wherein the second select transistor uses the second P +  drain/source doped region mutually with the second floating gate transistor; 
 wherein both the first P +  drain doped region and the second P +  drain doped region are connected to the same bit line. 
 
     
     
       2. The non-volatile single-poly memory cell for one bit storage of  claim 1 , wherein the non-volatile single-poly memory device further comprises a virtual symmetric line, the first unit cell and the second unit cell being symmetric mirror image to each other in relative to the virtual symmetric line. 
     
     
       3. The non-volatile single-poly memory cell for one bit storage of  claim 1 , wherein each of the select gate, the first floating gate and the second floating gate is composed of a single layer of polysilicon. 
     
     
       4. The non-volatile single-poly memory cell for one bit storage of  claim 1 , wherein both the first P +  source doped region and the second P +  source doped region are connected to the same source line. 
     
     
       5. The non-volatile single-poly memory cell for one bit storage of  claim 1 , wherein the first P +  source doped region is connected to a first source line and the second P +  source doped region is connected to a second source line, respectively. 
     
     
       6. The non-volatile single-poly memory cell for one bit storage of  claim 1 , wherein the first P +  drain/source doped region and the second P +  drain/source doped region are floating. 
     
     
       7. The non-volatile single-poly memory cell for one bit storage of  claim 1 , the first P +  drain/source doped region is connected to a first voltage signal and the second P +  drain/source doped region is connected to a second voltage signal, respectively.