Methods of manufacturing metal-silicide features

Abstract

A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.

1. A method of manufacturing a microelectronics device, comprising:
 forming a dielectric layer substantially surrounding a dummy feature located over a substrate; 
 removing the dummy feature to form an opening in the dielectric layer; and 
 forming a metal-silicide layer substantially conforming to the opening by co-flowing a gas comprising silicon during a metal deposition process, wherein the forming the metal-silicide layer includes varying a concentration gradient between a metal constituent and a silicide constituent to form a plurality of metal-silicide layers substantially conforming to the opening, wherein the plurality of metal-silicide layers exhibit varying work function levels. 
 
   
   
     2. The method of  claim 1  further comprising annealing the metal-silicide layer. 
   
   
     3. The method of  claim 1  wherein the metal-silicide layer comprises nickel silicide. 
   
   
     4. The method of  claim 1  wherein the metal-silicide layer comprises cobalt silicide. 
   
   
     5. The method of  claim 1  wherein the metal-silicide layer comprises tungsten silicide. 
   
   
     6. The method of  claim 1  wherein the gas comprising silicon is silane. 
   
   
     7. A method of manufacturing a microelectronics device, comprising:
 forming a dielectric layer substantially surrounding a dummy feature located over a substrate; 
 removing the dummy feature to form an opening in the dielectric layer; and 
 forming a metal-silicide layer substantially conforming to the opening by co-flowing a gas comprising silicon during a metal deposition process—wherein a concentration gradient between a metal constituent and a silicide constituent of the metal-silicide layer is varied, such that the metal-silicide layer exhibits a desired electrical characteristic.