Methods of forming phase change memory devices having bottom electrodes

Abstract

Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.

1. A method of fabricating a phase change memory device, comprising:
 forming line-shaped or L-shaped bottom electrodes in contact with respective bottom patterns on a substrate and having top surfaces defined by dimensions in x and y axes directions on the substrate, wherein the dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device; 
 forming phase change patterns in contact with the top surface of the bottom electrodes and having a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes; and 
 forming top electrodes on the phase change patterns, 
 wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction. 
 
     
     
       2. The method according to  claim 1 , wherein the dimension in y-axis direction of the top surface of the bottom electrodes has a width equal to or greater than the resolution limit of a photolithography process. 
     
     
       3. The method according to  claim 2 , wherein forming L-shaped bottom electrodes comprises:
 forming an interlayer insulating layer on the substrate having the bottom patterns; 
 forming line-shaped trenches extending in the y-axis direction and simultaneously exposing portions of the two bottom patterns neighboring in the x-axis direction within the interlayer insulating layer; 
 sequentially forming a bottom electrode layer and a spacer layer in the substrate having the line-shaped trenches; 
 sequentially etching-back the spacer layer and the bottom electrode layer to form L-shaped bottom electrode patterns and spacers; 
 forming first insulating patterns filling the line-shaped trenches in the substrate having the L-shaped bottom electrode patterns and the spacers; 
 forming line-shaped mask patterns extending in the x-axis direction on the substrate having the first insulating patterns and the L-shaped bottom electrode patterns; 
 etching the first insulating patterns, the L-shaped bottom electrode patterns, and the interlayer insulating layer until the bottom patterns are exposed using the line-shaped mask patterns as an etch mask; and 
 filling second insulating patterns in the etched region. 
 
     
     
       4. The method according to  claim 3 , further comprising:
 before forming the line-shaped mask patterns extending in the x-axis direction, planarizing the substrate having the first insulating patterns, the L-shaped bottom electrode patterns, and the spacers to planarize top surfaces of the L-shaped bottom electrode patterns. 
 
     
     
       5. The method according to  claim 2 , wherein forming L-shaped bottom electrodes comprises:
 forming an interlayer insulating layer on the substrate having the bottom patterns; 
 forming line-shaped trenches extending in the y-axis direction and simultaneously exposing portions of the two bottom patterns neighboring in the x-axis direction within the interlayer insulating layer; 
 forming bottom electrode patterns covering sidewalls and bottom surfaces of the line-shaped trenches; 
 forming internal insulating patterns filling the line-shaped trenches in the substrate having the bottom electrode patterns; 
 forming mask patterns having a first opening exposing a central region of the internal insulating patterns in the y-axis direction and a second opening exposing a top region between the bottom patterns in the x-axis direction, on the substrate having the internal insulating patterns and the bottom electrode patterns; 
 etching the internal insulating patterns, the bottom electrode patterns, and the interlayer insulating layer until the bottom patterns are exposed using the mask patterns as an etch mask; and 
 filling insulating patterns in the etched region. 
 
     
     
       6. The method according to  claim 1 , wherein forming line-shaped bottom electrodes comprises:
 forming an interlayer insulating layer on the substrate having the bottom patterns; 
 forming line-shaped trenches extending in the y-axis direction and simultaneously exposing portions of the two bottom patterns neighboring in the x-axis direction within the interlayer insulating layer; 
 forming bottom electrode spacers on sidewalls of the line-shaped trenches; 
 forming first insulating patterns in the line-shaped trenches in the substrate having the bottom electrode spacers; 
 forming line-shaped mask patterns extending in the x-axis direction on the substrate having the first insulating patterns, the bottom electrode spacers and the interlayer insulating layer; 
 etching the first insulating patterns, the bottom electrode spacers and the interlayer insulating layer until the bottom patterns are exposed using the line-shaped mask patterns as an etch mask; and 
 filling second insulating patterns in the etched region. 
 
     
     
       7. The method according to  claim 6 , wherein forming bottom electrode spacers comprises:
 forming a bottom electrode layer covering sidewalls and bottom surfaces of the line-shaped trenches and a top surface of the interlayer insulating layer; and 
 etching-back the bottom electrode layer. 
 
     
     
       8. The method according to  claim 6 , wherein forming first insulating patterns in the line-shaped trenches in the substrate having the bottom electrode spacers comprises:
 forming a first insulating layer on the substrate having the bottom electrode spacers; and 
 planarizing the first insulating layer to expose top surfaces of the bottom electrode spacers. 
 
     
     
       9. The method according to  claim 1 , wherein the dimension in the y-axis direction of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process. 
     
     
       10. The method according to  claim 9 , wherein forming line-shaped bottom electrodes comprises:
 forming an interlayer insulating layer on the substrate having the bottom patterns; 
 forming line-shaped trenches extending in the y-axis direction and simultaneously exposing portions of the two bottom patterns neighboring in the x-axis direction within the interlayer insulating layer; 
 forming bottom electrode spacers on sidewalls of the line-shaped trenches; 
 forming first insulating patterns filling the line-shaped trenches in the substrate having the bottom electrode spacers; 
 forming line-shaped sacrificial patterns extending in the x-axis direction on the substrate having the first insulating patterns, the bottom electrode spacers, and the interlayer insulating layer; 
 forming mask spacers on sidewalls of the line-shaped sacrificial patterns; 
 etching the line-shaped sacrificial patterns, the interlayer insulating layer, the bottom electrode spacers, and the first insulating patterns until the bottom patterns are exposed using the mask spacers as an etch mask; and 
 filling second insulating patterns in the etched region. 
 
     
     
       11. The method according to  claim 10 , wherein forming bottom electrode spacers comprises:
 forming a bottom electrode layer covering sidewalls and bottom surfaces of the line-shaped trenches and a top surface of the interlayer insulating layer; and 
 etching-back the bottom electrode layer. 
 
     
     
       12. The method according to  claim 10 , wherein the sidewalls of the line-shaped sacrificial patterns are formed above the respective bottom patterns. 
     
     
       13. The method according to  claim 9 , wherein the forming of the L-shaped bottom electrodes comprises:
 forming an interlayer insulating layer on the substrate having the bottom patterns; 
 forming line-shaped trenches extending in the y-axis direction and simultaneously exposing portions of the two bottom patterns neighboring in the x-axis direction within the interlayer insulating layer; 
 sequentially forming a bottom electrode layer and a spacer layer in the substrate having the line-shaped trenches; 
 sequentially etching-back the spacer layer and the bottom electrode layer to form L-shaped bottom electrode patterns and spacers; 
 forming first insulating patterns filling the line-shaped trenches in the substrate having the L-shaped bottom electrode patterns and the spacers; 
 forming line-shaped sacrificial patterns extending in the x-axis direction on the substrate having the first insulating patterns and the L-shaped bottom electrode patterns; 
 forming mask spacers on sidewalls of the line-shaped sacrificial patterns; 
 etching the line-shaped sacrificial patterns, the first insulating patterns, the L-shaped bottom electrode patterns, and the interlayer insulating layer until the bottom patterns are exposed using the mask spacers as an etch mask; and 
 filling second insulating patterns in the etched region. 
 
     
     
       14. The method according to  claim 13 , wherein the sidewalls of the line-shaped sacrificial patterns are formed above the respective bottom patterns. 
     
     
       15. The method according to  claim 1 , wherein the L-shaped bottom electrodes include a section of an L shape and a section of a symmetrical structure of the L shape. 
     
     
       16. The method according to  claim 15 , wherein the L-shaped bottom electrodes adjacent to each other have the symmetrical L-shaped structures. 
     
     
       17. The method according to  claim 1 , wherein the bottom patterns are formed of diodes. 
     
     
       18. The method according to  claim 1 , wherein the bottom patterns are formed of a contact plug in contact with the substrate and a conductive pattern disposed on the contact plug. 
     
     
       19. The method according to  claim 18 , further comprising:
 before forming the contact plug, forming transistors electrically connected to the respective bottom patterns on the substrate. 
 
     
     
       20. The method according to  claim 1 , wherein the phase change patterns extend in a direction parallel to the x-axis of the top surface of the bottom electrodes or extend in a direction parallel to the y-axis of the top surface of the bottom electrodes. 
     
     
       21. The method according to  claim 1 , wherein the phase change patterns and the top electrodes are simultaneously formed by patterning. 
     
     
       22. A method of fabricating a phase change memory device, comprising:
 preparing a substrate having bottom patterns; 
 forming an interlayer insulating layer on the substrate having the bottom patterns; 
 forming cylindrical bottom electrodes in contact with the bottom patterns through the interlayer insulating layer; 
 forming insulating patterns in the interlayer insulating layer to cut portions of the cylindrical bottom electrodes and the interlayer insulating layer in a vertical direction; 
 forming phase change patterns in contact with upper portions of the partially cut cylindrical bottom electrodes; and 
 forming top electrodes on the phase change patterns. 
 
     
     
       23. The method according to  claim 22 , wherein the partially cut cylindrical bottom electrodes have a crescent shape, a “C” shape, or a “(” shape from the top view. 
     
     
       24. The method according to  claim 22 , wherein the bottom patterns include diodes and diode electrodes which are sequentially stacked. 
     
     
       25. The method according to  claim 22 , wherein the bottom patterns include contact plugs in contact with the substrate and conductive patterns disposed on the contact plugs. 
     
     
       26. The method according to  claim 25 , further comprising forming transistors electrically connected to the respective bottom patterns on the substrate. 
     
     
       27. The method according to  claim 22 , wherein the forming of the insulating patterns comprises:
 cutting the portions of the cylindrical bottom electrodes and the interlayer insulating layer in a vertical direction to form trenches exposing portions of top surfaces of the bottom patterns and cut sidewalls of the partially cut cylindrical bottom electrodes; and 
 forming an insulating layer within the trenches. 
 
     
     
       28. The method according to  claim 22 , wherein the forming of the insulating patterns comprises:
 cutting the portions of the cylindrical bottom electrodes and the interlayer insulating layer in a vertical direction to form trenches exposing top surfaces and sidewalls of the cut portions of the partially cut cylindrical bottom electrodes; and 
 forming an insulating layer within the trenches. 
 
     
     
       29. The method according to  claim 22 , wherein the forming of the cylindrical bottom electrodes comprises:
 forming bottom electrode contact holes exposing top surfaces of the bottom patterns through the interlayer insulating layer; 
 forming a bottom electrode layer covering sidewalls and bottom surfaces of the bottom electrode contact holes on the interlayer insulating layer having the bottom electrode contact holes; 
 forming an internal insulating layer filling the bottom electrode contact holes on the substrate having the bottom electrode layer; and 
 planarizing the internal insulating layer and the bottom electrode layer until a top surface of the interlayer insulating layer is exposed. 
 
     
     
       30. The method according to  claim 29 , further comprising, after planarizing the internal insulating layer and the bottom electrode layer until the top surface of the interlayer insulating layer is exposed, performing a planarization process at least once. 
     
     
       31. A method of fabricating a phase change memory device, comprising:
 forming an interlayer insulating layer on a substrate having bottom patterns; 
 forming cylindrical bottom electrodes on the respective bottom patterns through the interlayer insulating layer; 
 forming line-shaped insulating patterns in the interlayer insulating layer in an x-axis or y-axis direction to removed portions of the cylindrical bottom electrodes and the interlayer insulating layer in a vertical direction; 
 forming phase change patterns in contact with partially removed cylindrical bottom electrodes on the partially removed cylindrical bottom electrodes; and 
 forming top electrodes on the respective phase change patterns. 
 
     
     
       32. The method according to  claim 31 , wherein the partially removed cylindrical bottom electrodes have a crescent shape, a “C” shape, or a “(” shape from the top view. 
     
     
       33. The method according to  claim 31 , wherein the same portions of the partially removed cylindrical bottom electrodes are cut to form a uniform CCC arrangement from the top view. 
     
     
       34. The method according to  claim 31 , wherein the phase change patterns are formed to extend in a direction parallel to or perpendicular to a surface along which the portions of the cylindrical bottom electrodes are cut. 
     
     
       35. The method according to  claim 31 , wherein the forming of the line-shaped insulating patterns comprises:
 cutting the portions of the cylindrical bottom electrodes and the interlayer insulating layer in a vertical direction to form line-shaped trenches exposing portions of top surfaces of the bottom patterns and cut sidewalls of the partially cut cylindrical bottom electrodes; and 
 forming an insulating layer within the line-shaped trenches. 
 
     
     
       36. The method according to  claim 31 , wherein the forming of the line-shaped insulating patterns comprises:
 cutting the portions of the cylindrical bottom electrodes and the interlayer insulating layer in a vertical direction to form line-shaped trenches exposing top surfaces and sidewalls of the cut portions of the partially cut cylindrical bottom electrodes; and 
 forming an insulating layer in the line-shaped trenches.