Halo-first ultra-thin SOI FET for superior short channel control

Abstract

Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

1. A semiconductor structure comprising:
 at least one patterned gate region located upon a surface of an ultra-thin semiconductor-on-insulator (UTSOI) layer, said UTSOI layer having a first portion that includes a a raised source/drain region located thereon and a second portion in which an extension ion implant region, a halo implant region and a device channel are located, said halo implant region and said extension implant region are laterally separated from each other by a distance from about 3 to about 20 nm thereby minimizing counter-doping in said extension implant region. 
 
     
     
       2. The semiconductor structure of  claim 1  wherein said UTSOI layer is located atop a buried insulating layer. 
     
     
       3. The semiconductor structure of  claim 1  wherein said UTSOI layer and said raised source/drain region are comprised of the same semiconductor material. 
     
     
       4. The semiconductor structure of  claim 1  further comprising a silicide region located on a surface of said raised source/drain region. 
     
     
       5. The semiconductor structure of  claim 1  wherein said patterned gate stack further includes a silicide region located atop a polysilicon gate conductor. 
     
     
       6. The semiconductor structure of  claim 1  wherein said halo implant region comprises boron ions in a concentration from about 3×10 18  atoms/cm 3  or greater. 
     
     
       7. The semiconductor structure of  claim 1  wherein said halo implant region comprises arsenic ions in a concentration from about 3×10 18  atoms/cm 3  or greater. 
     
     
       8. The semiconductor structure of  claim 1  wherein said UTSOI layer has a thickness of less than 20 nm. 
     
     
       9. The semiconductor structure of  claim 1  further comprising a gate passivation layer located on a portion of vertical sidewalls of said at least one patterned gate stack.