Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion

Abstract

A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

1. A multi-state low-current-switching magnetic memory element comprising:
 a free layer; 
 a first stack disposed upon a surface of the free layer; 
 a second stack disposed upon a surface of the free layer; 
 a magnetic tunneling junction disposed upon the free layer, between the first stack and the second stack; 
 wherein the first stack and second stack pin opposing magnetic moments within the free layer, creating two magnetic domains separated by a domain wall within the free layer; and 
 the position of the domain wall relative to the magnetic tunneling junction corresponds to different memory states. 
 
     
     
       2. A multi-state low-current-switching magnetic memory element of  claim 1 , wherein current passed between the stacks pushes the free layer domain wall. 
     
     
       3. A multi-state low-current-switching magnetic memory element of  claim 2 , wherein current passed between a stack and the magnetic tunnel junction provides a reading regarding the domain wall position. 
     
     
       4. A multi-state low-current-switching magnetic memory element of  claim 3 , wherein the reading of the domain wall position is a resistance value. 
     
     
       5. A multi-state low-current-switching magnetic memory element of  claim 4 , wherein different resistance values correspond to different memory states. 
     
     
       6. A multi-state low-current-switching magnetic memory element of  claim 5 , wherein the cross-sectional area of the free layer is about 500 nm 2  to 25,000 nm 2 .