Non-volatile memory devices and methods of manufacturing the same

Abstract

Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.

1. A non-volatile memory device comprising:
 a substrate; 
 a tunnel insulation layer on the substrate; 
 a floating gate on the tunnel insulation layer; 
 a gate insulation layer on the floating gate; 
 a low-dielectric constant (low-k) region between the floating gate and the gate insulation layer, the low-k region including a material having a dielectric constant less than silicon oxide and less than a dielectric constant of the gate insulation layer; and 
 a control gate on the gate insulation layer. 
 
     
     
       2. The device of  claim 1 , wherein the low-k region is an air spacer. 
     
     
       3. The device of  claim 1 , wherein the low-k region includes at least one of a silicon oxide fluoride and a silicon oxide carbide. 
     
     
       4. The device of  claim 1 , wherein the low-k region is on an upper surface of the floating gate and on at least one sidewall of the floating gate. 
     
     
       5. The device of  claim 4 , wherein the low-k region surrounds a top of the floating gate. 
     
     
       6. The device of  claim 1 , wherein a width of the low-k region is greater than a width of an upper surface of the floating gate in a channel width direction. 
     
     
       7. The device of  claim 1 , wherein a width of the low-k region is greater than a width of an upper surface of the floating gate in a channel length direction. 
     
     
       8. The device of  claim 7 , further comprising:
 an insulation spacer on a sidewall of the floating gate, 
 wherein the low-k region is between the insulation spacer and the floating gate. 
 
     
     
       9. The device of  claim 1 , wherein an uppermost surface of the low-k region is lower than an uppermost surface of the gate insulation layer, and a bottommost surface of the low-k region is higher than a bottommost surface of the gate insulation layer. 
     
     
       10. The device of  claim 1 , wherein the low-k region is defined by a top surface of the floating gate, a bottom surface of the gate insulation layer, and sidewalls of the gate insulation layer.