Semiconductor device conductive pattern structures including dummy conductive patterns

Abstract

Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

What is claimed is: 
     
       1. A conductive pattern structure of a semiconductor device comprising:
 a plurality of closely spaced-apart signal lines that extend in parallel from a first end of the semiconductor device to a second end of the semiconductor device that is opposite the first end; 
 a reference voltage pad that is wider than one of the closely spaced-apart signal lines and that extends from the first end of the semiconductor device to a middle portion of the semiconductor device but not to the second end of the semiconductor device; and 
 a dummy conductive line adjacent the reference voltage pad and that extends from the first end of the semiconductor device to the second end of the semiconductor device. 
 
     
     
       2. The conductive pattern structure of  claim 1  wherein the dummy conductive line is a first dummy conductive line, the conductive pattern structure further comprising:
 a plurality of closely spaced-apart second dummy conductive lines that extend in parallel from the second end of the semiconductor device towards the reference voltage pad. 
 
     
     
       3. The conductive pattern structure of  claim 2  wherein at least one of the second dummy conductive lines is electrically connected to the first dummy conductive line. 
     
     
       4. The conductive pattern structure of  claim 1  wherein the dummy conductive line is between the plurality of closely spaced-apart signal lines and the reference voltage pad. 
     
     
       5. The conductive pattern structure of  claim 2  wherein the signal lines, the first dummy conductive line and the second dummy conductive lines are of equal widths and are equally spaced apart. 
     
     
       6. The conductive pattern structure of  claim 2  further comprising a connector dummy conductive line that extends from the first dummy conductive line across the second dummy conductive lines. 
     
     
       7. The conductive pattern structure of  claim 2  wherein the signal lines, reference voltage pad, the first dummy conductive line and the second dummy conductive lines comprise copper. 
     
     
       8. The conductive pattern structure of  claim 1  wherein the dummy conductive line is a first dummy conductive line, the conductive pattern structure further comprising:
 a second dummy conductive line that extends orthogonally from the first dummy conductive line adjacent the reference voltage pad.