Test pattern generation for diagnosing scan chain failures

Abstract

Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. At least some embodiments can be used to locate faults over multiple capture cycles in the scan chain.

We claim: 
     
       1. A computer-implemented method comprising:
 generating one or more scan chain test patterns for locating a faulty scan cell in a scan chain in an electronic circuit by, for each respective one of the one or more scan chain test patterns, capturing a fault effect of the faulty scan cell after a plurality of capture cycles. 
 
     
     
       2. The method of  claim 1 , further comprising applying at least some of the generated one or more patterns to the electronic circuit to identify a range of one or more scan cell candidates containing the faulty scan cell. 
     
     
       3. The method of  claim 1 , wherein the faulty scan cell has a stuck-at fault. 
     
     
       4. The method of  claim 1 , wherein the faulty scan cell has a timing fault. 
     
     
       5. The method of  claim 4 , wherein the timing fault is one of a slow-to-rise fault, a slow-to-fall fault, a slow fault, a hold-time fault, a fast-to-rise fault, a fast-to-fall fault, and a fast fault. 
     
     
       6. The method of  claim 1 , wherein a first of the one or more scan chain test patterns is generated according to a first test pattern generation method, and wherein a second of the one or more scan chain test patterns is generated according to a second test pattern generation method. 
     
     
       7. One or more computer-readable storage media storing computer-executable instructions which, when executed by a computer, cause the computer to perform a method, the method comprising:
 generating one or more scan chain test patterns for locating a faulty scan cell in a scan chain in an electronic circuit by, for each respective one of the one or more scan chain test patterns, capturing a fault effect of the faulty scan cell after a plurality of capture cycles. 
 
     
     
       8. The one or more computer-readable storage media of  claim 7 , wherein the method further comprises applying at least some of the generated one or more patterns to the electronic circuit to identify a range of one or more scan cell candidates containing the faulty scan cell. 
     
     
       9. The one or more computer-readable storage media of  claim 7 , wherein the faulty scan cell has a stuck-at fault. 
     
     
       10. The one or more computer-readable storage media of  claim 7 , wherein the faulty scan cell has a timing fault. 
     
     
       11. The one or more computer-readable storage media of  claim 10 , wherein the timing fault is one of a slow-to-rise fault, a slow-to-fall fault, a slow fault, a hold-time fault, a fast-to-rise fault, a fast-to-fall fault, and a fast fault. 
     
     
       12. The one or more computer-readable storage media of  claim 7 , wherein a first of the one or more scan chain test patterns is generated according to a first test pattern generation method, and wherein a second of the one or more scan chain test patterns is generated according to a second test pattern generation method. 
     
     
       13. A system, comprising:
 a memory; and 
 a processor programmed to:
 generate one or more scan chain test patterns for locating a faulty scan cell in a scan chain in an electronic circuit by, for each respective one of the one or more scan chain test patterns, capturing a fault effect of the faulty scan cell after a plurality of capture cycles, and 
 store the one or more scan chain test patterns in the memory.