Formation of dividers between gate ends of field effect transistor devices

Abstract

A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.

What is claimed is: 
     
       1. A method for forming a semiconductor device, comprising:
 defining active regions on a substrate; 
 forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate; 
 removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks; 
 forming a gap-fill dielectric material from a first dielectric material over the exposed portions of the substrate; 
 removing portions of the gap-fill dielectric material to expose the dummy gate stacks; 
 removing the dummy gate stacks to form dummy gate trenches; 
 forming dividers from a second dielectric material within the dummy gate trenches, wherein portions of the dividers are formed over top surfaces of the gap-fill dielectric material; 
 depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material; and 
 removing portions of the gate stack material to define gate stacks, the gate stacks having a longitudinal axis along a first direction, wherein remaining portions of the gap-fill material the first dielectric material also have a longitudinal axis along the first direction, and wherein the dividers have a longitudinal axis in a second direction orthogonal to the first direction, and wherein locations of the plurality of dividers are independent from self-alignment to source and drain diffusion regions. 
 
     
     
       2. The method of  claim 1 , wherein the dummy gate stacks include a first dummy gate stack arranged in parallel to a second dummy gate stack. 
     
     
       3. The method of  claim 1 , wherein the dividers include a first divider arranged in parallel with respect to a second divider, the longitudinal axes of the first divider and the second divider arranged orthogonal to the longitudinal axis of the first dielectric material. 
     
     
       4. The method of  claim 1 , wherein the second dielectric material of the dividers is formed by an extreme ultraviolet (EUV) lithography process. 
     
     
       5. The method of  claim 1 , wherein the second dielectric material of the dividers includes a printable dielectric material formed by a lithographic process. 
     
     
       6. The method of  claim 1 , wherein the dividers include a hydrogen silsesquioxane material. 
     
     
       7. The method of  claim 1 , wherein the dividers include a methyl silsesquioxane material. 
     
     
       8. The method of  claim 1 , wherein the method further comprises implanting ions in exposed portions of source and drain regions prior to forming the dielectric material over the exposed portions of the substrate and the source and drain regions. 
     
     
       9. The method of  claim 1 , wherein the dummy gate stack material includes a polysilicon material. 
     
     
       10. The method of  claim 1 , wherein the dividers define a gap region between end portions of the gate stacks along a same longitudinal axis. 
     
     
       11. The method of  claim 1 , wherein a width of the dividers defines a gap region between the end portions of the gate stacks along a same longitudinal axis. 
     
     
       12. The method of  claim 1 , wherein the active regions include a first source and drain region and a second source and drain region, the first source and drain region arranged in parallel to the second source and drain region. 
     
     
       13. The method of  claim 1 , further comprising defining source and drain regions by forming a first source and drain region and a second source and drain region in a silicon material on the substrate. 
     
     
       14. The method of  claim 1 , wherein the removal of the dummy gate stacks exposes a channel region.