Ion implanted and self aligned gate structure for GaN transistors

Abstract

A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.

What is claimed is: 
     
       1. A transistor comprising:
 a substrate; 
 transition material formed over the substrate; 
 a buffer material formed over the transition material; 
 a barrier material formed over the buffer material; 
 a gate layer formed over the barrier material; 
 a dielectric layer with an opening formed over the gate layer; 
 a gate metal formed in the opening of the dielectric layer, the gate metal being self-aligned with a gate region; and 
 source and drain contacts, 
 wherein the gate layer comprises a doped portion defining the gate region that is disposed under the opening of the dielectric layer and an undoped portion outside of the gate region adapted to reduce current leakage, and 
 wherein the doped portion defining the gate region is doped with implanted ions from a group consisting of Mg, Fe, V, Cr and C. 
 
     
     
       2. The transistor of  claim 1 , wherein the gate metal comprises one of TiN, Ta, TaN, Pd, W, WSi2, Ni and Au. 
     
     
       3. The transistor of  claim 1 , wherein the barrier material comprises AlGaN. 
     
     
       4. The transistor of  claim 1 , wherein sides of the gate have an angle of about 90 degrees with respect to the gate layer. 
     
     
       5. The transistor of  claim 1 , wherein sides of the gate are not perpendicular to the gate layer. 
     
     
       6. The transistor of  claim 1 , wherein insulating material is formed on sides of the gate metal. 
     
     
       7. The transistor of  claim 1 , wherein the gate metal is TiN. 
     
     
       8. A method of forming a transistor with a self-aligned gate, the method comprising:
 forming transition layers on a substrate; 
 forming a GaN buffer layer over the transition layers; 
 forming a barrier layer over the GaN buffer layer; 
 forming a gate layer over the barrier layer, wherein the gate layer is undoped; 
 forming a dielectric layer over the gate layer; 
 forming an opening through the dielectric layer to the gate layer to expose a portion of the gate layer; 
 performing an ion implantation process containing p-type impurities through the opening in the dielectric layer to form an ion implanted region of the gate layer, wherein the ion implanted region defines a gate region and a non-ion implanted region outside the gate region for reducing current leakage; 
 forming a gate metal material over the gate region using the opening through the dielectric layer to define a gate metal that is self-aligned with the gate region; and 
 forming Ohmic drain and source contact regions. 
 
     
     
       9. The method of  claim 8 , further comprising an activation process after the ion implantation process. 
     
     
       10. The method of  claim 9 , wherein the activation process comprises a rapid thermal annealing process. 
     
     
       11. The method of  claim 8 , wherein the ion implantation process implants ions selected from the group consisting of Mg, Fe, V, Cr and C. 
     
     
       12. The method of  claim 8 , wherein the gate metal comprises one of TiN, Ta, TaN, Pd, W, WSi2, Ni and Au. 
     
     
       13. The method of  claim 8 , wherein the barrier layer comprises AlGaN. 
     
     
       14. The method of  claim 8 , wherein sides of the gate have an angle of about 90 degrees with respect to the gate layer. 
     
     
       15. The method of  claim 8 , wherein sides of the gate are not perpendicular to the gate material. 
     
     
       16. The method of  claim 8 , wherein insulating material is formed on sides of the gate metal to form spacers to further reduce leakage current. 
     
     
       17. The method of  claim 8 , wherein the gate metal is TiN.