Composite layer stacking for enhancement mode transistor

Abstract

A transistor includes a first layer of a first type disposed over a buffer layer and having a first concentration of a first material. A first layer of a second type is disposed over the first layer of the first type, and a second layer of the first type is disposed over the first layer of the second type. The second layer of the first type having a second concentration of a first material that is greater than the first concentration of the first material. A source and a drain are spaced laterally from one another and are disposed over the buffer layer. A gate disposed over at least a portion of the second layer of the first type and disposed within a recessed area defined by the first and second layers of the first type and the first layer of the second type.

What is claimed is: 
     
       1. A transistor, comprising:
 a first layer of a first type disposed over a buffer layer, the first layer of the first type having a first concentration of a first material; 
 a first layer of a second type disposed over the first layer of the first type; 
 a second layer of the first type disposed over the first layer of the second type, the second layer of the first type having a second concentration of the first material that is greater than the first concentration of the first material; 
 a source and a drain laterally spaced from one another and disposed over the buffer layer; and 
 a gate disposed over at least a portion of the second layer of the first type and disposed within a recessed area defined by the first and second layers of the first type and the first layer of the second type such that at least a portion of the first layer of the first type is interrupted by the gate. 
 
     
     
       2. The transistor of  claim 1 , wherein the buffer layer is formed over a semiconductor substrate. 
     
     
       3. The transistor of  claim 1 , wherein the gate is disposed over a dielectric layer that is disposed over the portion of the second layer of the first type and disposed within the recessed area defined by the first and second layers of the first type and the first layer of the second type. 
     
     
       4. The transistor of  claim 1 , wherein the first layer of the first type includes aluminum gallium nitride. 
     
     
       5. The transistor of  claim 4 , wherein the first concentration is in a range from 0.07 to 0.15 percent by weight, and the first material is aluminum. 
     
     
       6. The transistor of  claim 4 , wherein the second concentration is in a range from 0.21 to 0.50 percent by weight, and the first material is aluminum. 
     
     
       7. The transistor of  claim 4 , wherein the first layer of the second type includes aluminum nitride. 
     
     
       8. The transistor of  claim 1 , wherein the first layer of the first type has a thickness of 5 nm along a length of the recessed area. 
     
     
       9. The transistor of  claim 1 , wherein the gate includes a conductive material disposed over a dielectric material. 
     
     
       10. A method, comprising:
 forming a first layer of a first type over a buffer layer, the first layer of the first type having a first concentration of a first material; 
 forming a first layer of a second type over the first layer of the first type; 
 forming a second layer of the first type over the first layer of the second type, the second layer of the first type having a second concentration of the first material that is greater than the first concentration of the first material; 
 forming a source and a drain over the buffer layer such that they are spaced laterally from one another; and 
 forming a recessed area through the first layer of the second type and the second layer of the first type and at least partially through the first layer of the first type; and 
 forming a gate over at least a portion of the second layer of the first type and within the recessed area. 
 
     
     
       11. The method of  claim 10 , further comprising forming the buffer layer over a substrate. 
     
     
       12. The method of  claim 10 , further comprising depositing a dielectric layer over at least a portion of the second layer of the first type and within the recessed area before the gate is formed. 
     
     
       13. The method of  claim 10 , wherein
 the first layer of the first type includes aluminum gallium nitride, 
 the first material is aluminum, 
 the first concentration is in a range from 0.07 to 0.15 percent by weight, and 
 the second concentration is in a range from 0.21 to 0.50 percent by weight. 
 
     
     
       14. A semiconductor device, comprising:
 a buffer layer disposed over a semiconductor substrate; 
 a first layer of a first type disposed over the buffer layer and having a first concentration of a first material; 
 a first layer of a second type disposed over the first layer of the first type; 
 a second layer of the first type disposed over the first layer of the second type and having a second concentration of the first material that is greater than the first concentration of the first material; 
 a source and a drain laterally spaced from one another and disposed over the buffer layer; and 
 a gate disposed over at least a portion of the second layer of the first type and disposed within a recessed area defined by the first and second layers of the first type and the first layer of the second type such that a bottom surface of the gate is disposed below an upper surface of the first layer of the first type. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the gate is disposed over a dielectric layer that disposed over the portion of the second layer of the first type and disposed within the recessed area defined by the first and second layers of the first type and the first layer of the second type such that a bottom-most surface of the dielectric layer is disposed above a bottom surface of the first layer of the first type. 
     
     
       16. The semiconductor device of  claim 14 , wherein the first layer of the first type includes aluminum gallium nitride. 
     
     
       17. The semiconductor device of  claim 16 , wherein the first concentration is in a range from 0.07 to 0.15 percent by weight, and the first material is aluminum. 
     
     
       18. The semiconductor device of  claim 16 , wherein the second concentration is in a range from 0.21 to 0.50 percent by weight, and the first material is aluminum. 
     
     
       19. The semiconductor device of  claim 16 , wherein the first layer of the second type includes aluminum nitride. 
     
     
       20. The semiconductor device of  claim 14 , wherein the first layer of the first type has a thickness of 5 nm along a length of the recessed area. 
     
     
       21. The semiconductor device of  claim 14 , further comprising an isolation region formed around a periphery of the enhancement-mode transistor.