Reducing gate height variance during semiconductor device formation

Abstract

In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

What is claimed is: 
     
       1. A method for reducing gate height variance in a semiconductor device, comprising:
 removing a hard mask layer and a set of spacers from a set of dummy gates, the removal of the hard mask layer and the set of spacers resulting in exposed surfaces comprising substantially an entirety of a top surface of each dummy gate of the set of dummy gates and at least a portion of side surfaces of each dummy gate; 
 depositing a liner layer and an inter-layer dielectric (ILD) over the set of dummy gates, the liner layer covering substantially an entirety of the exposed surfaces of each dummy gate; 
 removing the liner layer from substantially all of the top surface of the set of dummy gates; and 
 removing the set of dummy gates. 
 
     
     
       2. The method of  claim 1 , the semiconductor device comprising a transistor. 
     
     
       3. The method of  claim 2 , the transistor comprising:
 a substrate; 
 a NFET region formed over the substrate; and 
 a PFET region formed over the substrate. 
 
     
     
       4. The method of  claim 3 , further comprising:
 a set of reversely switched dinistors (RSDs) in the NFET region; and 
 a set of silicon germanium (SiGe) regions in the PFET region. 
 
     
     
       5. The method of  claim 1 , the set of dummy gates comprising poly silicon. 
     
     
       6. The method of  claim 1 , the liner layer comprising nitride. 
     
     
       7. The method of  claim 1 , further comprising polishing the ILD. 
     
     
       8. The method of  claim 1 , the liner layer being removed via polishing or etching. 
     
     
       9. The method of  claim 1 , further comprising a semiconductor device formed according to the method of  claim 1 . 
     
     
       10. A method for reducing gate height variance in a semiconductor device, comprising:
 removing a hard mask layer and a set of spacers from a first gate stack and a second gate stack, the first gate stack having a first dummy gate, and the second gate stack having a second dummy gate, the removal of the hard mask layer and the set of spacers resulting in exposed surfaces comprising substantially an entirety of a top surface of each of the first and second dummy gates and at least a portion of side surfaces of each of the first and second dummy gates; 
 depositing a liner layer and an inter-layer dielectric (ILD) over the first dummy gate and the second dummy gate, the liner layer covering substantially an entirety of the exposed surfaces of each of the first and second dummy gates; 
 removing the liner layer from substantially all of the top surface of the first dummy gate and the second dummy gate; and 
 removing the set of dummy gates to reduce a height variance between the first gate stack and the second gate stack. 
 
     
     
       11. The method of  claim 10 , the semiconductor device comprising a transistor. 
     
     
       12. The method of  claim 11 , the transistor comprising:
 a substrate; 
 a NFET region formed over the substrate; and 
 a PFET region formed over the substrate. 
 
     
     
       13. The method of  claim 12 , further comprising:
 a set of reversely switched dinistors (RSDs) in the NFET region; and 
 a set of silicon germanium (SiGe) regions in the PFET region. 
 
     
     
       14. The method of  claim 10 , the set of dummy gates comprising poly silicon. 
     
     
       15. The method of  claim 10 , the liner layer comprising nitride. 
     
     
       16. The method of  claim 10 , further comprising polishing the ILD. 
     
     
       17. The method of  claim 10 , the liner layer being removed via polishing or etching. 
     
     
       18. The method of  claim 10 , further comprising a semiconductor device formed according to the method of  claim 1 . 
     
     
       19. A method for reducing gate height variance in a semiconductor device, comprising:
 identifying a height variance between a first gate stack and a second gate stack of a semiconductor device, the first gate stack having a first dummy gate and the second gate stack having a second dummy gate; 
 removing a hard mask layer and a set of spacers from the first gate stack and the second gate stack, the removal of the hard mask layer and the set of spacers resulting in exposed surfaces comprising substantially an entirety of a top surface of each of the first and second dummy gates and at least a portion of side surfaces of each of the first and second dummy gates; 
 depositing a liner layer and an inter-layer dielectric (ILD) over the first dummy gate and the second dummy gate, the liner layer covering substantially an entirety of the exposed surfaces of each of the first and second dummy gates; 
 removing the liner layer from at least substantially all of the top surface of the first dummy gate and the second dummy gate; and 
 removing the set of dummy gates to reduce the height differential between the first gate stack and the second gate stack. 
 
     
     
       20. The method of  claim 19 , further comprising a semiconductor device formed according to the method of  claim 1 .