P
US8933542B2ActiveUtilityPatentIndex 84

Method to reduce magnetic film stress for better yield

Assignee: HEADWAY TECHNOLOGIES INCPriority: May 11, 2012Filed: Aug 7, 2014Granted: Jan 13, 2015
Est. expiryMay 11, 2032(~5.8 yrs left)· nominal 20-yr term from priority
Inventors:ZHONG TOMHUANG KENLINTORNG CHYU-JIUH
H01L 43/12H10N 50/01
84
PatentIndex Score
12
Cited by
7
References
6
Claims

Abstract

A thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate, is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer on the CMOS substrate is patterned by either undercut trenches extending into its upper surface or by T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A thin-film deposition comprising:
 a substrate: 
 a pattern of walls formed on the substrate; 
 a multi-layered thin-film deposition formed on said substrate, wherein said thin-film deposition is broken into segments by said pattern of walls and wherein said thin-film deposition is subsequently processed; whereby 
 process-induced stresses are relieved by said pattern of walls; and 
 said thin-film deposition is free of defects normally caused by said process-induced stresses. 
 
     
     
       2. The thin-film deposition of  claim 1  wherein said substrate is a CMOS substrate and wherein said multi-layered thin-film deposition is an MTJ deposition. 
     
     
       3. The thin-film deposition of  claim 2  wherein said CMOS substrate has a last metal layer and a connection via and interface layer formed on said last metal layer and wherein said pattern of walls is formed on said via and interface layer. 
     
     
       4. The thin-film deposition of  claim 1  wherein said walls are T-shaped in vertical cross-section, having a wide base supported by a narrow pedestal. 
     
     
       5. The thin-film deposition of  claim 3  wherein said walls have a wide base portion formed of a first dielectric material having a low etch rate and wherein said wide base portion is supported on a narrow pedestal portion formed of a second dielectric material having a high etch rate. 
     
     
       6. The thin-film deposition of  claim 5  wherein said second dielectric material is the high etch rate material amorphous carbon, porous dielectric material or other spin-on filler materials that etch rapidly under N 2  or oxygen plasmas and wherein said first dielectric material is SiN, SiO 2  or any other material that does not etch using an oxygen or N 2  plasma.

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