Contact structure for a semiconductor device and methods of making same

Abstract

A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.

What is claimed: 
     
       1. A device, comprising:
 first and second spaced-apart active regions positioned in a semiconducting substrate; 
 an isolation region positioned between and separating said first and second spaced-apart active regions; 
 a layer of gate insulation material positioned on said first active region; and 
 a first conductive line feature extending continuously from said first active region and across said isolation region to said second active region, said first conductive line feature comprising a first portion that is positioned directly above said layer of gate insulation material positioned on said first active region and a second portion that conductively contacts said second active region. 
 
     
     
       2. The device of  claim 1 , wherein said first conductive line feature comprises polysilicon. 
     
     
       3. The device of  claim 1 , wherein said first conductive line feature comprises at least one layer of metal and a layer of polysilicon, and wherein one of said at least one layer of metal and said layer of polysilicon conductively contacts said second active region. 
     
     
       4. The device of  claim 1 , wherein said first conductive line feature comprises a plurality of layers of metal, and wherein at least one of said plurality of layers of metal conductively contacts said second active region. 
     
     
       5. The device of  claim 1 , wherein said first conductive line feature is a gate electrode for a pull-up transistor of an SRAM device, said pull-up transistor being positioned in and above said first active region. 
     
     
       6. The device of  claim 1 , further comprising a third active region that is spaced apart from said first and second active regions and separated from said first and second active regions by said isolation region, wherein said first conductive line feature is a shared gate electrode for a pull-up transistor and a pull-down transistor of an SRAM device, said pull-up transistor being positioned in and above said first active region and said pull-down transistor being positioned in and above said third active region. 
     
     
       7. The device of  claim 1 , further comprising a pull-up transistor for an SRAM device, wherein said pull-up transistor is positioned in and above said second active region and comprises a second conductive line feature that is a gate electrode for said pull-up transistor. 
     
     
       8. The device of  claim 1 , wherein said first conductive line feature has an end surface that is positioned above said second active region, the device further comprising a sidewall spacer positioned on said end surface of said first conductive line feature. 
     
     
       9. The device of  claim 1 , further comprising a doped source/drain region positioned in said second active region and a contact doped region positioned in said second active region under said second portion of said first conductive line feature. 
     
     
       10. The device of  claim 1 , further comprising a conductive contact that is conductively coupled to an upper surface of said first conductive line feature. 
     
     
       11. A device, comprising:
 first and second spaced-apart active regions positioned in a semiconducting substrate; 
 an isolation region positioned between and separating said first and second spaced-apart active regions; 
 a layer of gate insulation material positioned on said first active region; 
 a first conductive line feature extending continuously from said first active region and across said isolation region to said second active region, said first conductive line feature comprising a first portion positioned directly above said layer of gate insulation material positioned on said first active region and a second portion that conductively contacts said second active region, said first conductive line feature having an end surface that is positioned above said second active region; 
 a sidewall spacer positioned on said end surface of said first conductive line feature; 
 a doped source/drain region positioned in said second active region; and 
 a contact doped region positioned in said second active region under said second portion of said first conductive line feature. 
 
     
     
       12. The device of  claim 11 , wherein said first conductive line feature is a gate electrode for a pull-up transistor of an SRAM device, said pull-up transistor being positioned in and above said first active region. 
     
     
       13. The device of  claim 11 , further comprising a third active region that is spaced apart from said first and second active regions and separated from said first and second active regions by said isolation region, wherein said first conductive line feature is a shared gate electrode for a pull-up transistor and a pull-down transistor of an SRAM device, said pull-up transistor being positioned in and above said first active region and said pull-down transistor in and above said third active region. 
     
     
       14. The device of  claim 11 , further comprising a pull-up transistor for an SRAM device, wherein said pull-up transistor is positioned in and above said second active region and comprises a second conductive line feature that is a gate electrode for said pull-up transistor. 
     
     
       15. The device of  claim 11 , further comprising a conductive contact that is conductively coupled to an upper surface of said first conductive line feature. 
     
     
       16. An SRAM device, comprising:
 first and second spaced-apart active regions positioned in a semiconducting substrate; 
 an isolation region positioned between and separating said first and second spaced-apart active regions; 
 a first pull-up transistor positioned in and above said first active region, said first pull-up transistor comprising a first gate insulation layer positioned on said first active region; 
 a first conductive line feature extending continuously from said first active region and across said isolation region to said second active region, said first conductive line feature comprising at least one layer of conductive material, wherein a first portion of said first conductive line feature is positioned directly above said first gate insulation layer of said first pull-up transistor positioned on said first active region and a second portion of said first conductive line feature conductively contacts said second active region; 
 a second pull-up transistor positioned in and above said second active region, said second pull-up transistor comprising a second gate insulation layer positioned on said second active region; and 
 a second conductive line feature extending continuously from said second active region and across said isolation region to said first active region, said second conductive line feature comprising at least one layer of conductive material, wherein a first portion of said second conductive line feature is positioned directly above said second gate insulation layer of said second pull-up transistor positioned on said second active region and a second portion of said second conductive line feature conductively contacts said first active region. 
 
     
     
       17. The device of  claim 16 , wherein said first and second conductive line features comprise polysilicon. 
     
     
       18. The device of  claim 16 , wherein said first and second conductive line features each comprise at least one layer of metal and a layer of polysilicon, and wherein one of said at least one layer of metal and said layer of polysilicon conductively contacts said second and first active regions, respectively. 
     
     
       19. The device of  claim 16 , wherein said first and second conductive line features each comprise a plurality of layers of metal, and wherein at least one of said plurality of layers of metal comprising said first and second conductive line features conductively contacts said second and first active regions, respectively. 
     
     
       20. The device of  claim 16 , further comprising a third active region that is spaced apart from said first and second active regions and a first pull-down transistor of said SRAM device that is positioned in and above said third active region, wherein said first conductive line feature is a shared gate electrode for said first pull-up transistor and said first pull-down transistor of said SRAM device. 
     
     
       21. The device of  claim 20 , further comprising a fourth active region that is spaced apart from said first and second active regions and a second pull-down transistor of said SRAM device that is positioned in and above said fourth active region, wherein said second conductive line feature is a shared gate electrode for said second pull-up transistor and said second pull-down transistor of said SRAM device. 
     
     
       22. The device of  claim 16 , wherein said first conductive line feature has an end surface that is positioned above said second active region, the device further comprising a sidewall spacer positioned on said end surface of said first conductive line feature. 
     
     
       23. The device of  claim 16 , further comprising a doped source/drain region positioned in said second active region and a contact doped region positioned in said second active region under said second portion of said first conductive line feature. 
     
     
       24. The device of  claim 16 , further comprising a conductive contact that is conductively coupled to an upper surface of said first conductive line feature.