Three-dimensional semiconductor devices with current path selection structure

Abstract

Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

What is claimed is: 
     
       1. A three-dimensional semiconductor memory device, comprising:
 a common source structure, a string selection structure, and a memory structure on a substrate, the memory structure interposed between the common source structure and the string selection structure, 
 wherein the memory structure comprises a plurality of sequentially stacked active patterns elongated parallel to a top surface of the substrate and including first and second end-portions, gate patterns extending perpendicular to the top surface of the substrate, and memory elements interposed between the active patterns and the gate patterns, and 
 wherein the string selection structure comprises:
 drain patterns elongated perpendicular to the top surface of the substrate to connect the first end-portions of the active patterns to each other; and 
 layer-selection patterns sequentially stacked to control an energy band structure of respective ones of the first end-portions of the sequentially stacked active patterns located at a same level. 
 
 
     
     
       2. The device of  claim 1 , wherein the drain patterns comprise a semiconductor material in direct contact with sidewalls of the first end-portions of the active patterns and having the same conductivity type as the active patterns. 
     
     
       3. The device of  claim 2 , wherein the drain patterns comprise an n- or p-type highly-doped semiconductor material, and
 the active patterns comprise a lightly-doped semiconductor material having the same conductivity type as the drain patterns. 
 
     
     
       4. The device of  claim 1 , wherein the layer-selection patterns comprise a semiconductor material in direct contact with end walls of the first end-portions of the active patterns and having a different conductivity type from the active patterns. 
     
     
       5. The device of  claim 4 , wherein the drain patterns comprise a semiconductor material being in direct contact with sidewalls of the first end-portions of the active patterns having a different conductivity type from the active patterns, and
 the drain patterns have an impurity concentration higher than the first end-portions of the active patterns. 
 
     
     
       6. The device of  claim 1 , wherein the string selection structure further comprises a string selection insulating layer electrically insulating sidewalls and end walls of the first end-portions of the active patterns from the layer-selection patterns. 
     
     
       7. The device of  claim 6 , wherein each of the layer-selection patterns and first end-portions of the active patterns located adjacent thereto are configured as metal-oxide-semiconductor (MOS) capacitors. 
     
     
       8. The device of  claim 1 , wherein the active patterns are arranged in horizontal and vertical directions to have a multi-layered and multi-column structure, and
 a respective one of the drain patterns is provided between a corresponding pair of columns of the active patterns. 
 
     
     
       9. The device of  claim 8 , wherein a respective one of the drain patterns is connected in common to a plurality of the first end-portions of the active patterns that constitute a corresponding one of the columns and are arranged at different levels from each other. 
     
     
       10. The device of  claim 8 , wherein a respective one of the layer-selection patterns is connected in common to a plurality of the first end-portions of the active patterns that constitute a corresponding one of the layers and are arranged at different columns from each other. 
     
     
       11. The device of  claim 1 , wherein the drain patterns are connected to sidewalls of the first end-portions of the active patterns, and wherein the layer-selection patterns are connected to end walls of the first end-portions of the active patterns. 
     
     
       12. The device of  claim 11  wherein the drain patterns are directly connected to the sidewalls of the first end-portions of the active patterns. 
     
     
       13. The device of  claim 12  wherein the layer-selection patterns are directly connected to the end walls of the first end-portions of the active patterns. 
     
     
       14. The device  claim 12  further comprising a string selection insulating layer on the end walls of the first end-portions of the active patterns, wherein the layer-selection patterns are on the string selection insulating layer opposite the end walls of the first end-portions of the active patterns. 
     
     
       15. A three-dimensional semiconductor memory device, comprising:
 a first layer comprising first and second active patterns; 
 a second layer comprising third and fourth active patterns; 
 wherein the first through fourth active patterns each include first and second end-portions; 
 a first drain pattern connected to the first and third active patterns at the first end-portions thereof; 
 a second drain pattern connected to the second and fourth active patterns at the first end-portions thereof; 
 a first layer-selection pattern connected to the first and second active patterns at the first end-portions thereof and configured to control depths of depletion regions in the first and second active patterns; and 
 a second layer-selection pattern connected to the third and fourth active patterns at the first end-portions thereof and configured to control depths of depletion regions in the third and fourth active patterns. 
 
     
     
       16. The device of  claim 15 , wherein the first drain patterns comprise a semiconductor material in direct contact with sidewalls of the first end-portions of the first and third active patterns and having a same conductivity type as the first end-portions of the first and third active patterns, and
 the second drain patterns comprises a semiconductor material in direct contact with sidewalls of the first end-portions of the second and fourth active patterns and having a same conductivity type as the first end-portions of the second and fourth active patterns. 
 
     
     
       17. The device of  claim 15 , wherein the first and second drain patterns comprise an n- or p-type semiconductor material, and
 the first end-portions of the first to fourth active patterns comprise a semiconductor material having the same conductivity type as the first and second drain patterns. 
 
     
     
       18. The device of  claim 15 , wherein the first layer-selection pattern comprises a semiconductor material in direct contact with end walls of the first end-portions of the first and second active patterns and having a different conductivity type from the first end-portions of the first and second active patterns. 
     
     
       19. The device of  claim 18 , wherein the first drain patterns comprise a semiconductor material in direct contact with sidewalls of the first end-portions of the first and third active patterns and having a same conductivity type as the first end-portions of the first and third active patterns,
 the second drain patterns comprise a semiconductor material in direct contact with sidewalls of the first end-portions of the second and fourth active patterns and having a same conductivity type as the first end-portions of the second and fourth active patterns, and 
 each of the first and second drain patterns have an impurity concentration higher than the first end-portions of the first to fourth active patterns. 
 
     
     
       20. A three-dimensional semiconductor memory device, comprising:
 a common source structure, a string selection structure, and a memory structure on a substrate, the memory structure interposed between the common source structure and the string selection structure, 
 wherein the memory structure comprises a plurality of sequentially stacked active patterns elongated parallel to a top surface of the substrate and including first and second end-portions, gate patterns extending perpendicular to the top surface of the substrate, and memory elements interposed between the active patterns and the gate patterns, 
 wherein the string selection structure is configured to select a plurality of the memory elements at a given level relative to the top surface of the substrate, while simultaneously refraining from selecting other memory elements that overlie or underlie the plurality of memory elements at the given level, and 
 wherein the string selection structure comprises: 
 drain patterns elongated perpendicular to the top surface of the substrate to connect the first end-portions of the active patterns to each other; and 
 layer-selection patterns sequentially stacked on the substrate adjacent the first end-portions. 
 
     
     
       21. The device of  claim 20 , wherein the active patterns are arranged in horizontal and vertical directions to have a multi-layered and multi-column structure, and
 each of the drain patterns is provided between a corresponding pair of columns of the active patterns. 
 
     
     
       22. The device of  claim 21 , wherein each of the drain patterns is connected in common to a plurality of sidewalls of the active patterns that constitute a corresponding one of the columns and are arranged at different levels from each other. 
     
     
       23. A three-dimensional semiconductor memory device, comprising:
 a common source structure, a string selection structure, and a memory structure on a substrate, the memory structure interposed between the common source structure and the string selection structure, 
 wherein the memory structure comprises a plurality of sequentially stacked active patterns elongated parallel to a top surface of the substrate and including first and second end-portions, gate patterns extending perpendicular to the top surface of the substrate, and memory elements interposed between the active patterns and the gate patterns, and 
 wherein the string selection structure comprises:
 drain patterns elongated perpendicular to the top surface of the substrate to connect sidewalls of the first end-portions of the active patterns to each other; and 
 layer-selection patterns sequentially stacked and connected to end walls of the first end-portions located at a same level to control an energy band structure of respective ones of the first end-portions of the sequentially stacked active patterns located at the same level. 
 
 
     
     
       24. The device of  claim 23  wherein the drain patterns are directly connected to the sidewalls of the first end-portions of the active patterns. 
     
     
       25. The device of  claim 24  wherein the layer-selection patterns are directly connected to the end walls of the first end-portions of the active patterns. 
     
     
       26. The device  claim 24  further comprising a string selection insulating layer on the end walls of the first end-portions of the active patterns, wherein the layer-selection patterns are on the string selection insulating layer opposite the end walls of the first end-portions of the active patterns.