Manufacturing methods semiconductor packages including through mold connectors

Abstract

A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

What is claimed is: 
     
       1. A semiconductor package comprising:
 a first semiconductor chip and a plurality of first bumps disposed on a first interconnection structure layer; 
 a first mold layer including a first portion and a second portion that form a stepped shape, the first portion covering the first semiconductor chip, the second portion filling between the first bumps to expose top portions of the first bumps; 
 second bumps connected to the exposed first bumps; 
 a second mold layer filling between each of the second bumps and filling the stepped shape to expose the top portions of the second bumps; 
 a second interconnection structure layer connected to the second bumps; 
 a second semiconductor chip mounted on the second interconnection structure laver; and 
 a third mold layer covering the second semiconductor chip. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein each of the first bumps has a lower height than an arrangement height of the first semiconductor chip. 
     
     
       3. The semiconductor package of  claim 1 , wherein the first and second bumps have a ball shape. 
     
     
       4. The semiconductor package of  claim 1 , wherein the first and second bumps include a solder ball having the substantially same diameter. 
     
     
       5. The semiconductor package of  claim 1 , wherein a height of the laminated first and second bumps is higher than the arrangement height of the first semiconductor chip. 
     
     
       6. The semiconductor package of  claim 1 , wherein the first interconnection structure layer includes a printed circuit board (PCB) or an interposer. 
     
     
       7. The semiconductor package of  claim 1 , further comprises third bumps electrically connecting the second interconnection structure layer to the exposed top portions of the second bumps for electrically connecting the second interconnection structure layer to the second bumps. 
     
     
       8. The semiconductor package of  claim 1 , further comprises a third semiconductor chip laminated on the second semiconductor chip and covered by the third mold layer. 
     
     
       9. The semiconductor package of  claim 1 ,
 wherein the semiconductor package has a package on package (PoP) structure, the PoP structure includes a first semiconductor package portion including the first interconnection structure layer and the first semiconductor chip and a second semiconductor package portion including the second interconnection structure layer and the second semiconductor chip, and the second semiconductor package portion is electrically connected to the first semiconductor package portion by a through mold connector including the second bumps laminated on the first bumps. 
 
     
     
       10. A semiconductor package comprising:
 a first mold layer including a first portion and a second portion, the first portion covering a first semiconductor chip, the second portion filling between a plurality of first bumps spaced apart from the first semiconductor chip in a lateral direction to expose top portions of the first bumps, and the first portion and the second portion forming a stepped shape; 
 second bumps connected to the exposed first bumps; 
 a second mold layer filling between the second bumps to expose the top portions of the second bumps and filling the stepped shape; 
 a first interconnection structure layer electrically connected to the first bumps; 
 a second interconnection structure layer connected to the second bumps; 
 a second semiconductor chip mounted on the second interconnection structure layer; and 
 a third mold layer covering the second semiconductor chip, 
 wherein the second bumps disposed on the first bumps form a through mold connector substantially penetrating the first and second mold layers. 
 
     
     
       11. The semiconductor package of  claim 10 , further comprises:
 a third bumps electrically connecting the second bumps to the second interconnection structure layer.