Semiconductor package and manufacturing method thereof

Abstract

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.

What is claimed is: 
     
       1. A semiconductor package comprising:
 a substrate comprising a top substrate surface, a bottom substrate surface, substrate sides between the top and bottom substrate surfaces, and a first bond pad on the top substrate surface; 
 a semiconductor die comprising a top die surface, a bottom die surface, die sides between the top and bottom die surfaces, and a second bond pad on the top die surface, where the bottom die surface is mounted on the top substrate surface; 
 a dielectric layer having a single layer of a single dielectric material on the substrate and the semiconductor die, where the dielectric layer comprises:
 a top dielectric layer surface; 
 a bottom dielectric layer surface on at least the top substrate surface and the top die surface; 
 a first dielectric layer aperture that extends from the top dielectric layer surface to the first bond pad; and 
 a second dielectric layer aperture that extends from the top dielectric layer surface to the second bond pad; 
 
 a conductive layer on the dielectric layer that extends between and electrically connects the first and second bond pads; and 
 a seed layer between the conductive layer and the dielectric layer. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the dielectric layer directly contacts the top substrate surface and the top die surface. 
     
     
       3. The semiconductor package of  claim 1 , wherein the substrate comprises a semiconductor die. 
     
     
       4. The semiconductor package of  claim 3 , wherein the semiconductor die comprises semiconductor circuitry. 
     
     
       5. The semiconductor package of  claim 1 , wherein the bottom die surface is mounted directly to the top substrate surface. 
     
     
       6. The semiconductor package of  claim 1 , wherein the bottom die surface is mounted directly to the top substrate surface utilizing an adhesive. 
     
     
       7. The semiconductor package of  claim 1 , wherein each of the first and second dielectric layer apertures comprises a sloped sidewall. 
     
     
       8. The semiconductor package of  claim 1 , wherein the dielectric layer comprises a dielectric layer side surface between the top dielectric layer surface and the bottom dielectric layer surface, and the dielectric layer side surface is coplanar with one of the substrate sides. 
     
     
       9. The semiconductor package of  claim 1 , comprising a conductive attachment structure electrically coupled to the conductive layer and positioned vertically above the substrate, and wherein the semiconductor package is free of conductive attachment structures positioned vertically below the substrate. 
     
     
       10. The semiconductor package of  claim 1 , comprising a conductive attachment structure connected to the conductive layer at a position laterally between the first bond pad and the second bond pad. 
     
     
       11. A semiconductor package comprising:
 a substrate comprising a top substrate surface, a bottom substrate surface, substrate sides between the top and bottom substrate surfaces, and a first bond pad on the top substrate surface; 
 a semiconductor die comprising a top die surface, a bottom die surface, die sides between the top and bottom die surfaces, and a second bond pad on the top die surface, where the bottom die surface is mounted on the top substrate surface; 
 a first dielectric layer having a single layer of a single dielectric material on the substrate and the semiconductor die, where the first dielectric layer comprises:
 a first top dielectric layer surface; 
 a first bottom dielectric layer surface on at least the top substrate surface and the first top die surface; 
 a first dielectric layer aperture that extends from the first top dielectric layer surface to the first bond pad; and 
 a second dielectric layer aperture that extends from the first top dielectric layer surface to the second bond pad; 
 
 a conductive layer on the first dielectric layer that extends between and electrically connects the first and second bond pads; 
 a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises:
 a second top dielectric layer surface; 
 a second bottom dielectric layer surface on at least the first top dielectric layer surface; and 
 a third dielectric layer aperture that extends from the second top dielectric layer surface to the conductive layer; 
 
 a conductive attachment structure; and 
 an underbump metallization (UBM) between the conductive attachment structure and the conductive layer, 
 wherein an uppermost surface of the UBM is lower than an uppermost surface of the second dielectric layer. 
 
     
     
       12. The semiconductor package of  claim 11 , wherein the third dielectric layer aperture is positioned laterally between the first and second dielectric layer apertures. 
     
     
       13. The semiconductor package of  claim 11 , wherein the substrate comprises semiconductor material. 
     
     
       14. The semiconductor package of  claim 11 , wherein the second dielectric layer fills a portion of the first dielectric layer aperture. 
     
     
       15. The semiconductor package of  claim 11 , wherein:
 the first dielectric layer comprises a first dielectric layer side surface between the first top dielectric layer surface and the first bottom dielectric layer surface; 
 the second dielectric layer comprises a second dielectric layer side surface between the second top dielectric layer surface and the second bottom dielectric layer surface; and 
 the first and second dielectric layer side surfaces are coplanar with one of the substrate sides. 
 
     
     
       16. The semiconductor package of  claim 11 , wherein the substrate is formed independently of the semiconductor die prior to coupling the bottom die surface and the top substrate surface. 
     
     
       17. A semiconductor package comprising:
 a substrate comprising a top substrate surface, a bottom substrate surface, substrate sides between the top and bottom substrate surfaces, and a first bond pad on the top substrate surface; 
 a semiconductor die comprising a top die surface, a bottom die surface, die sides between the top and bottom die surfaces, and a second bond pad on the top die surface, where the bottom die surface is mounted directly to the top substrate surface with an adhesive layer; 
 a dielectric layer of a single layer of a single dielectric material on the substrate and the semiconductor die, where the dielectric layer comprises:
 a top dielectric layer surface; 
 a bottom dielectric layer surface on at least the top substrate surface and the top die surface; 
 a first dielectric layer aperture that extends from the top dielectric layer surface to the first bond pad; and 
 a second dielectric layer aperture that extends from the top dielectric layer surface to the second bond pad; and 
 
 a conductive layer on the dielectric layer that extends between and electrically connects the first and second bond pads, 
 wherein a portion of the dielectric layer is positioned directly laterally between the adhesive layer and the first bond pad. 
 
     
     
       18. The semiconductor package of  claim 17 , wherein the dielectric layer directly contacts side surfaces of the adhesive layer. 
     
     
       19. The semiconductor package of  claim 17 , wherein the adhesive layer does not extend laterally beyond the die sides. 
     
     
       20. The semiconductor package of  claim 17 , comprising a conductive attachment structure electrically coupled to the conductive layer and positioned vertically above the substrate, and wherein the semiconductor package is free of conductive attachment structures positioned vertically below the substrate. 
     
     
       21. A semiconductor package comprising:
 a substrate comprising a top substrate surface, a bottom substrate surface, substrate sides between the top and bottom substrate surfaces, and a first bond pad on the top substrate surface; 
 a semiconductor die comprising a top die surface, a bottom die surface, die sides between the top and bottom die surfaces, and a second bond pad on the top die surface, where the bottom die surface is mounted on the top substrate surface; 
 a dielectric layer having a single layer of a single dielectric material on the substrate and the semiconductor die, where the dielectric layer comprises:
 a top dielectric layer surface; 
 a bottom dielectric layer surface on at least the top substrate surface and the top die surface; 
 a first dielectric layer aperture that extends from the top dielectric layer surface to the first bond pad; and 
 a second dielectric layer aperture that extends from the top dielectric layer surface to the second bond pad; and 
 
 a conductive layer on the dielectric layer that extends between and electrically connects the first and second bond pads, 
 wherein the substrate comprises a semiconductor die. 
 
     
     
       22. The semiconductor package of  claim 21 , wherein the semiconductor die comprises semiconductor circuitry.