Precise junction placement in vertical semiconductor devices using etch stop layers

Abstract

A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

What is claimed is: 
     
       1. A method of fabricating a vertical fin field effect transistor (FinFET) comprising;
 forming a first source/drain region having a majority composition of a first semiconductor material, said forming the first source/drain region comprising epitaxially growing a first portion of said first semiconductor material that is in situ doped atop a strain relaxed buffer layer; epitaxially growing a semiconductor etch stop layer on the first portion of the first semiconductor material; and epitaxially growing a second portion of said first semiconductor material that is in situ doped atop the semiconductor etch stop layer, wherein the semiconductor etch stop layer is of a second semiconductor material having a different etch selectively than the first semiconductor material; 
 forming a material layer stack including at least a channel semiconductor material atop the first source/drain region of the device; 
 etching the material layer stack to provide a channel region selectively to the semiconductor etch stop layer, wherein a depth of the semiconductor etch stop layer dictates overlap between said first source/drain region and the channel region of the device; and 
 forming a gate structure on the channel region. 
 
     
     
       2. The method of  claim 1 , wherein the semiconductor etch stop layer comprises an indium and phosphorus containing material. 
     
     
       3. The method of  claim 1 , wherein said etching the material layer stack to provide a channel region selectively to the semiconductor etch stop layer comprises:
 etching the material stack selectively to the first portion of the first of the source and the drain region; and 
 etching the first portion of the first source/drain region selectively to the semiconductor etch stop layer, wherein an etched first portion of the first of source/drain region has a width equal to a width of the channel semiconductor material, wherein the etched first portion of the first source/drain region that has been etched provides an extension region for the first source/drain region that overlaps with the channel region. 
 
     
     
       4. The method of  claim 3 , wherein the material stack comprises a second source/drain region atop the channel semiconductor material. 
     
     
       5. The method of  claim 4 , wherein forming the gate structure comprises:
 forming a first spacer on the first source/drain region; 
 forming a gate dielectric layer on the channel region; 
 forming a gate conductor on the gate dielectric and overlying the first spacer; and 
 forming a second spacer on the gate conductor, wherein the overlap between said first of the source and drain region and the channel region of the device is a portion of the first source/drain region that extends past the interface surface of the first spacer with the recessed surface of the first source/drain region. 
 
     
     
       6. The method of  claim 4 , wherein the first source/drain region and the second source/drain region have a same conductivity type. 
     
     
       7. A method of fabricating a vertical tunnel field effect transistor (tunnel FET) comprising;
 forming a first source/drain region having a majority composition of a first semiconductor material and a first conductivity type, said forming the first source/drain region comprising epitaxially growing a first portion of said first semiconductor material that is in situ doped atop a strain relaxed buffer layer, epitaxially growing a semiconductor etch stop layer on the first portion of the first semiconductor material, and epitaxially growing a second portion of said first semiconductor material that is in situ doped atop the semiconductor etch stop layer, wherein the semiconductor etch stop layer of the second semiconductor material has a different etch selectively than the first semiconductor material; 
 forming a material stack including at least a channel semiconductor material atop the first of the source and drain region of the device; 
 etching the material stack to provide a channel region selectively to the semiconductor etch stop layer, wherein a depth of the semiconductor etch stop layer dictates overlap between said first of the source and drain region and the channel region of the device; 
 forming a second of the source and the drain region having a second conductivity type positioned on the channel region opposite the first of the source and the drain region; and 
 forming a gate structure on the channel region. 
 
     
     
       8. The method of  claim 7 , wherein the first semiconductor material comprises a type III-V semiconductor material. 
     
     
       9. The method of  claim 8 , wherein the semiconductor etch stop layer comprises an indium and phosphorus containing material. 
     
     
       10. The method of  claim 7 , wherein said etching the material layer stack to provide a channel region selectively to the semiconductor etch stop layer comprises:
 etching the material stack selectively to the first portion of the first source/drain region; and 
 etching the first portion of the first source/drain region selectively to the semiconductor etch stop layer, wherein an etched first portion of the first source/drain region has a width equal to a width of the channel semiconductor material, wherein the etched first portion of the first source/drain region that has been etched provides an extension region for the first source/drain region that overlaps with the channel region. 
 
     
     
       11. The method of  claim 10 , wherein the material stack comprises a second source/drain region atop the channel semiconductor material.