FinFET with high mobility and strain channel

Abstract

An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

What is claimed is: 
     
       1. An integrated circuit device, comprising:
 a fin extending in a first direction out from a substrate, the fin having a first end and a second end opposite the first end and a center region interposed between the first end and the second end; 
 a gate structure extending over the center region; 
 a recess in the first end of the fin, the recess having substantially straight sidewalls; 
 a first layer lining the substantially straight sidewalls of the recess, the first layer forming a substantially straight interface with a channel region defined under the gate structure, the first layer being conformal along the substantially straight interface; and 
 a source/drain region within the lined recess. 
 
     
     
       2. The integrated circuit device of  claim 1 , wherein the source/drain region is doped with a dopant, and the first layer reduces out diffusion of the dopant. 
     
     
       3. The integrated circuit device of  claim 2 , wherein the dopant comprises boron or phosphorous. 
     
     
       4. The integrated circuit device of  claim 1 , wherein the first layer is configured to provide strain to the center region. 
     
     
       5. The integrated circuit device of  claim 1 , further comprising one or more second layers interposed between the first layer and the source/drain region. 
     
     
       6. An integrated circuit device comprising:
 a fin extending from a substrate; 
 a gate structure extending over the fin; 
 a source/drain region in a recess in the fin; and 
 a liner separating the source/drain region from the fin, a vertical interface between the source/drain region and the liner being substantially parallel to a sidewall of the gate structure. 
 
     
     
       7. The integrated circuit device of  claim 6 , wherein an upper surface of the recess is non-perpendicular relative to an upper surface of the fin. 
     
     
       8. The integrated circuit device of  claim 7 , wherein an angle between the upper surface of the recess and the upper surface of the fin is less than or equal to seventy degrees. 
     
     
       9. The integrated circuit device of  claim 6 , wherein the liner is a conformal layer. 
     
     
       10. The integrated circuit device of  claim 6 , wherein a length of a vertical sidewall of the liner is equal to or greater than one half of a depth of a gate area of the fin below the gate structure. 
     
     
       11. The integrated circuit device of  claim 6 , wherein the liner comprises a first liner and a second liner interposed between the first liner and the source/drain region, wherein the second liner comprises a different material than the first liner. 
     
     
       12. The integrated circuit device of  claim 11 , wherein the liner further comprises a third liner interposed between the second liner and the source/drain region. 
     
     
       13. The integrated circuit device of  claim 6 , wherein the liner exerts a tensile or compressive stress to the fin under the gate structure. 
     
     
       14. The integrated circuit device of  claim 6 , wherein a first thickness of the liner along a vertical sidewall of the recess is less than a second thickness of the liner along a bottom of the recess. 
     
     
       15. An integrated circuit device, comprising:
 a fin extending in a first direction out from a substrate, the fin having a first end and a second end opposite the first end and a center region interposed between the first end and the second end; 
 a gate structure extending over the center region; 
 a first recess in the first end of the fin, the first recess having a first substantially straight sidewall; 
 a first layer lining the first substantially straight sidewall of the first recess, the first layer forming a substantially straight interface with the fin, the first layer being conformal along the substantially straight interface; and 
 a source/drain region within the lined recess. 
 
     
     
       16. The integrated circuit device of  claim 15 , wherein the source/drain region is doped with a dopant, and the first layer reduces out diffusion of the dopant. 
     
     
       17. The integrated circuit device of  claim 15 , wherein the first layer exerts stress a channel region under the gate structure. 
     
     
       18. The integrated circuit device of  claim 15 , wherein the first layer comprises a lightly doped drain. 
     
     
       19. The integrated circuit device of  claim 15 , wherein the first layer has a thickness between 5 nm and 50 nm.