Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages

Abstract

In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V CC -V th , while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2·V CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

What is claimed is: 
     
       1. A semiconductor memory device of a column select line system, comprising: a memory array divided into a plurality of memory array portions;   means for selectively accessing any of said plurality of memory array portions;   a plurality of bit line pairs for reading data for respective columns from each of said memory array portions;   an I/O line pair selectively connected with the plurality of bit line pairs of each of said memory array portions; and   means provided for each said memory array portion i) for precharging said bit line pairs and said I/O line pair to a potential 1/2Vcc in non-access time of said memory array portion, and   ii) for precharging said bit line pairs to the potential of 1/2Vcc and said I/O line pair to a potential different from 1/2Vcc in access time of said memory array.     
     
     
       2. The semiconductor memory device according to claim 1, wherein said means for precharging precharges said I/O line pair to a higher potential than the potential of said bit line pairs in access time of said memory array portion.   
     
     
       3. A random access memory, comprising: a plurality of memory array portions arranged to constitute one memory array as a whole, each of said plurality of memory array portions including a plurality of memory cells arranged two-dimensionally in rows and columns;   a plurality of bit line pairs provided for each said memory array portion for reading data from respective columns of said memory cells constituting each said memory array portion;   a plurality of amplifying means for amplifying, respectively, data read via said plurality of bit line pairs;   an I/O line pair provided for each said memory array portion for receiving data from said plurality of bit line pairs;   a plurality of gate means provided for each said memory array portion for connecting said plurality of bit line pairs to said I/O line pair;   means responsive to a row address signal for activating any of said plurality of memory array portions so as to read data from any of said memory cells included in the activated memory array portion onto a corresponding one of said bit line pairs;   column decoder means responsive to a column address signal for controlling, in common, opening and closing of said plurality of gate means corresponding to a common column address in the respective memory array portions;   first precharge means provided for each said memory array portion for precharging said bit line pairs to a first potential independently of access time/non-access time of said memory array portion; and   second precharge means provided for each said memory array portion for precharging said I/O line pair to said first potential in non-access time of said memory array portion and for precharging said I/O line pair to a second potential different from said first potential in access time of said memory array portion.   
     
     
       4. The random access memory according to claim 3, wherein said second potential is set to be higher than said first potential.   
     
     
       5. The random access memory according to claim 4, wherein said first potential is 1/2 of a predetermined supply potential, and said second potential is an arbitrary potential between said first potential and said supply potential. .Iadd.   
     
     
       6.  A random access memory having a standby state and an active state, comprising: a memory array having a plurality of memory array portions each including a bit line pair, each of said plurality of memory array portions having an access state and a nonaccess state, said plurality of memory array portions being in said nonaccess state when said random access memory is in said standby state, a memory array portion of said plurality of memory array portions being in said access state and other memory array portion of said plurality of memory array portions being in said nonaccess state when said random access memory is in said active state;   a plurality of I/O line pairs corresponding to said plurality of memory array portions;   a column select line provided in common to said plurality of memory array portions;   a plurality of gate means corresponding to said plurality of memory array portions, said plurality of gate means commonly coupled to said column select line, each of said gate means responsive to a signal transmitted by said column select line for coupling the bit line pair included in a corresponding memory array portion to the I/O line pair corresponding to said corresponding memory array portion;   a plurality of first charging means coupled to said plurality of I/O line pairs respectively, each of said plurality of first charging means for providing a first potential to the I/O line pair coupled to said each first charging means when the memory array portion corresponding to said I/O line pair coupled to said each first charging means is in said nonaccess state, said first potential having a same potential level as a precharge potential for precharging said bit line pairs;   a plurality of second charging means coupled to said plurality of I/O line pairs respectively, each of said plurality of second charging means for precharging the I/O line pair coupled to said each second charging means to a second potential when the memory array portion corresponding to said I/O line pair coupled to said each second charging means is in said access state, said second potential being different from said first potential; and   a plurality of preamplifiers corresponding to said plurality of I/O line pairs respectively, each of said plurality of preamplifiers for outputting data responsive to a potential difference appearing on a corresponding I/O line pairs, said potential difference being smaller than a difference between power supply potential and ground potential. .Iaddend..Iadd.7. A random access memory having a standby state and an active state, comprising:   a memory array having a plurality of memory array portions each including a bit line pair, each of said plurality of memory array portions having an access state and a nonaccess state, said plurality of memory array portions being in said nonaccess state when said random access memory is in said standby state, a memory array portion of said plurality of memory array portions being in said access state and other memory array portion of said plurality of memory array portions being in said nonaccess state when said random access memory is in said active state;   a plurality of I/O line pairs corresponding to said plurality of memory array portions;   a column select line provided in common to said plurality of memory array portions;   a plurality of gate means corresponding to said plurality of memory array portions, said plurality of gate means commonly coupled to said column select line, each of said gate means responsive to a signal transmitted by said column select line for coupling the bit line pair included in a corresponding memory array portion to the I/O line pair corresponding to said corresponding memory array portion;   a plurality of charging means coupled to said plurality of I/O line pairs respectively, each of said plurality of charging means for providing a first potential to the I/O line pair coupled to said each charging means when the memory array portion corresponding to said I/O line pair coupled to said each charging means is in said nonaccess state, said first potential having a same potential level as a precharge potential for precharging said bit line pairs; and   a plurality of load means coupled to said plurality of I/O line pairs respectively, each of said plurality of load means for providing a second potential to the I/O line pair coupled to said each load means during the memory array portion corresponding to said I/O line pair coupled to said each load means is in said access state, said second Potential being   
     
     
        different from said first potential. .Iaddend..Iadd.8.  A random access memory having a standby state and an active state, comprising: a memory array having a plurality of memory array portions each including a bit line pair, each of said plurality of memory array portions having an access state and a nonaccess state, said plurality of memory array portions being in said nonaccess state when said random access memory is in said standby state, a memory array portion of said plurality of memory array portions being in said access state and other memory array portion of said plurality of memory array portions being in said nonaccess state when said random access memory is in said active state;   a plurality of I/O line pairs corresponding to said plurality of memory array portions;   a column select line provided in common to said plurality of memory array portions;   a plurality of gate means corresponding to said plurality of memory array portions, said plurality of gate means commonly coupled to said column select line, each of said gate means responsive to a signal transmitted by said column select line for coupling the bit line pair included in a corresponding memory array portion to the I/O line pair corresponding to said corresponding memory array portion;   a plurality of first charging means coupled to said plurality of I/O line pairs respectively, each of said plurality of first charging means for providing a first potential to the I/O line pair coupled to said each first charging means when the memory array portion corresponding to said I/O line pair coupled to said each first charging means is in said nonaccess state, said first potential having a same potential level as a precharge potential for precharging said bit line pairs; and   a plurality of second charging circuits corresponding to said plurality of I/O line pairs respectively, each of said plurality of second charging circuits including a first N channel MOS transistor and a second N channel MOS transistor, said first N channel MOS transistor coupled between a power supply node and one I/O line of a corresponding I/O line pair, said second N channel MOS transistor coupled between said power supply node and another I/O line of said corresponding I/O line pair, said first and second MOS transistor turned on for precharging said corresponding I/O line pair to a second potential when the memory array portion corresponding to said corresponding I/O line pair is in said access state, said second potential being a potential which is lower than a power supply potential provided to said power supply node by a threshold voltage of said first and second N channel MOS transistors. .Iaddend.