Method to control gate CD

Abstract

The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.

1. A process to control line width after etching, comprising:
 providing a mask generation data file, including data on lines having a first minimum width;  
 modifying the data file whereby said first minimum width is increased by an amount;  
 from said modified file, forming a reticle;  
 coating a semiconductor wafer, having a top layer, with photoresist and then exposing said photoresist to an image of said reticle and then developing the photoresist to form a photoresist image;  
 inspecting said photoresist image thereby determining a second minimum width;  
 based on the difference between the first and second minimum widths, generating a control sequence for photoresist trimming;  
 then trimming the photoresist image according to said control sequence; and  
 then etching said top layer, using the trimmed photoresist image as a mask.  
 
     
     
       2. The process of  claim 1  wherein said first minimum width is between about 0.14 and 0.18 microns. 
     
     
       3. The process of  claim 1  wherein said second minimum width is between about 0.12 and 0.16 microns. 
     
     
       4. The process of  claim 1  wherein the amount by which the first minimum width is increased is between about 0.01 and 0.03 microns. 
     
     
       5. The process of  claim 1  wherein said trimming control sequence further comprises using a mixture of chlorine and oxygen gases, in a conductive or inductive etcher, at a power level between about 200 and 300 watts, for between about 20 and 60 seconds. 
     
     
       6. The process of  claim 1  wherein the coating of photoresist has a thickness between about 0.3 and 0.5 microns. 
     
     
       7. A process to reduce edge roughness of lines in a photoresist pattern, comprising:
 providing a mask generation data file, including data on lines having a first minimum width;  
 modifying the data file whereby said first minimum width is increased by an amount;  
 from said modified file, forming a reticle;  
 coating a semiconductor wafer, having a top layer, with photoresist and then exposing said photoresist to an image of said reticle and then developing the photoresist to form a photoresist image of the lines;  
 inspecting said photoresist image thereby determining a second minimum width;  
 based on the difference between the first and second minimum widths, generating a control sequence for photoresist trimming; and  
 then trimming the photoresist image according to said control sequence, thereby reducing edge roughness of the lines.  
 
     
     
       8. The process of  claim 7  wherein the lines in the photoresist image, prior to trimming, have an edge roughness between about 15 and 25 nm. 
     
     
       9. The process of  claim 7  wherein the lines in the photoresist image, after trimming, have an edge roughness between about 10 and 15 nm. 
     
     
       10. The process of  claim 7  wherein said trimming control sequence further comprises using a mixture of chlorine and oxygen gases, in a conductive or inductive etcher, at a power level between about 200 and 300 wafts, for between about 20 and 60 seconds. 
     
     
       11. A process for width control of a polysilicon gate, comprising:
 providing a mask generation data file, including data on lines having a first minimum width;  
 modifying the data file whereby said first minimum width is increased by an amount;  
 from said modified file, forming a reticle;  
 providing a semiconductor wafer having a top layer of polysilicon  
 depositing a layer of a hard mask material on said polysilicon layer;  
 coating the hard mask layer with photoresist and then exposing said photoresist to an image of said reticle and then developing the photoresist to form a photoresist image;  
 inspecting said photoresist image thereby determining a second minimum width;  
 based on the difference between the first and second minimum widths, generating a control sequence for photoresist trimming;  
 then trimming the photoresist image according to said control sequence;  
 then etching said hard mask layer, using the trimmed photoresist image as a mask, thereby forming a hard mask; and  
 then etching the polysilicon layer to form a gate.  
 
     
     
       12. The process of  claim 11  wherein the amount by which the first minimum width is increased is between about 0.01 and 0.03 microns. 
     
     
       13. The process of  claim 11  wherein said trimming control sequence further comprises using a mixture of chlorine and oxygen gases, in a conductive or inductive etcher, at a power level between about 200 and 300 watts, for between about 20 and 60 seconds. 
     
     
       14. The process of  claim 11  wherein the polysilicon layer has a thickness between about 0.15 and 0.35 microns. 
     
     
       15. The process of  claim 11  wherein the hard mask layer is selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. 
     
     
       16. The process of  claim 11  wherein the hard mask layer has a thickness between about 0.04 and 0.08 microns. 
     
     
       17. A process to reduce edge roughness of a semiconductor gate line, having a first width, comprising:
 providing a mask generation data file, including data on said first the gate width;  
 modifying the data file whereby said first line width is increased by an amount;  
 from said modified file, forming a reticle;  
 providing a semiconductor wafer having a top layer of polysilicon  
 depositing a layer of a hard mask material on said polysilicon layer;  
 coating the hard mask layer with photoresist and then exposing said photoresist to an image of said reticle and then developing the photoresist to form a photoresist image;  
 inspecting said photoresist image thereby determining a second gate width;  
 based on the difference between the first and second gate widths, generating a control sequence for photoresist trimming;  
 then trimming the photoresist image according to said control sequence;  
 then etching said hard mask layer, using the trimmed photoresist image as a mask, thereby forming a hard mask; and  
 then etching the polysilicon layer to form a gate having reduced edge roughness.  
 
     
     
       18. The process of  claim 17  wherein the lines in the photoresist image, prior to trimming, have an edge roughness between about 15 and 25 nm. 
     
     
       19. The process of  claim 17  wherein the lines in the photoresist image, after trimming, have an edge roughness between about 10 and 15 nm. 
     
     
       20. The process of  claim 17  wherein said trimming control sequence further comprises using a mixture of chlorine and oxygen gases, in a conductive or inductive etcher, at a power level between about 200 and 300 watts, for between about 20 and 60 seconds. 
     
     
       21. A process to etch, in a layer having an upper surface, a pattern that includes lines having a target width, comprising:
   providing a reticle that includes a pattern of lines having a line width greater than the target width;        coating said upper surface with a layer of photoresist;        exposing said photoresist layer to an image projected from said reticle;        developing said photoresist layer, whereby a photoresist pattern, that includes lines having a developed width that is greater than said target width, is formed;        trimming said photoresist pattern according to a control sequence based on the difference between said developed width and said target width, thereby forming lines having said target width; and        etching said layer, using said trimmed photoresist pattern as a mask.     
     
     
       22. The process described in  claim 21  further comprising:
   providing a mask generation data file that includes data on lines having a given minimum width;        modifying said data file whereby said given minimum width is increased by an amount; and        using said modified data file to form said line pattern on said reticle.     
     
     
       23. The process of  claim 21  wherein said amount by which said given minimum width is increased between about  0 . 01  and  0 . 03  microns. 
     
     
       24. The process of  claim 21  wherein said trimming control sequence further comprises using a mixture of chlorine and oxygen gases. 
     
     
       25. The process of  claim 21  wherein etching said layer comprises using a conductive or inductive etcher at a power level between about  200  and  300  watts. 
     
     
       26. A method comprising:
   receiving a photolithography mask generation data file that includes data on a pattern having lines of a given minimum width;        modifying said mask generation data file whereby said given minimum width is increased by a  predetermined amount; and      using said modified mask generation data file to form a line pattern on a mask having a line width greater than a target critical dimension of a semiconductor pattern.