In-situ strip process for polysilicon etching in deep sub-micron technology

Abstract

A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for MOS devices. A hard mask layer is provided overlying the polysilicon layer. A resist layer is provided overlying the hard mask layer. The resist layer is patterned to form a resist mask the exposes a part of the hard mask layer. The polysilicon layer is patterned in a plasma dry etching chamber. First, the resist layer is optionally trimmed by etching. Second, the hard mask layer is etched where exposed by the resist mask to form a hard mask that exposes a part of the polysilicon layer. Third, the resist mask is stripped away. Fourth, polymer residue from the resist mask is cleaned away using a chemistry containing CF 4 gas. Fifth, the polysilicon layer is etched where exposed by the hard mask. After the polysilicon layer is so patterned in the dry plasma etch chamber, the hard mask layer is stripped away to complete the patterning of the polysilicon layer in the manufacture of the integrated circuit device.

1. A method to pattern a polysilicon layer in the manufacture of an integrated circuit device comprising:
 providing a polysilicon layer overlying a semiconductor substrate;  
 providing a hard mask layer overlying said polysilicon layer;  
 providing a resist layer overlying said hard mask layer;  
 patterning said resist layer to form a resist mask that exposes a part of said hard mask layer;  
 patterning said polysilicon layer wherein said patterning is performed sequentially in a dry plasma etch chamber and wherein said patterning comprises: 
 etching said hard mask layer exposed by said resist mask to form a hard mask that exposes a part of said polysilicon layer;  
 thereafter stripping away said resist mask;  
 thereafter cleaning away polymer residue from said hard mask wherein said cleaning away comprises a chemistry containing CF 4  gas; and  
 thereafter etching said polysilicon layer exposed by said hard mask; and  
 
 stripping away said hard mask to complete the patterning of said polysilicon layer in the manufacture of the integrated circuit device.  
 
     
     
       2. The method according to  claim 1  wherein said hard mask layer comprises silicon oxynitride. 
     
     
       3. The method according to  claim 1  wherein said step of etching said hard mask layer comprises a chemistry containing CF 4  gas. 
     
     
       4. The method according to  claim 1  wherein said step of stripping away said resist mask comprises a chemistry containing O 2  gas. 
     
     
       5. The method according to  claim 1  wherein said step of etching said polysilicon layer comprises a main etch step followed by an overetch step. 
     
     
       6. The method according to  claim 1  wherein said step of etching said polysilicon layer comprises a chemistry of: HBr gas, Cl 2  gas, He—O 2  gas, and combinations thereof. 
     
     
       7. The method according to  claim 1  further comprising providing a silicon dioxide layer overlying said hard mask layer and underlying said resist layer. 
     
     
       8. The method according to  claim 1  further comprising etching said resist layer to trim said resist layer prior to said step of etching said hard mask layer wherein said etching of said resist layer is performed in said dry plasma etching chamber. 
     
     
       9. The method to pattern a polysilicon layer in the manufacture of an integrated circuit device comprising:
 providing a polysilicon layer overlying a semiconductor substrate;  
 providing a hard mask layer overlying said polysilicon layer;  
 providing a silicon dioxide layer said hard mask layer;  
 providing a resist layer overlying said hard mask layer;  
 patterning said resist layer to form a resist mask that exposes a part of said hard mask layer;  
 patterning said polysilicon layer wherein said patterning is performed sequentially in a dry plasma etch chamber and wherein said patterning comprises: 
 etching said resist mask to trim said resist mask;  
 thereafter etching said hard mask layer exposed by said resist mask to form a hard mask that exposes a part of said polysilicon layer;  
 thereafter stripping away said resist mask;  
 thereafter cleaning away polymer residue from said resist mask wherein said cleaning away comprises a chemistry containing CF 4  gas; and  
 thereafter etching said polysilicon layer exposed by said hard mask; and  
 
 stripping away said hard mask to complete the patterning of said polysilicon layer in the manufacture of the integrated circuit device.  
 
     
     
       10. The method according to  claim 9  wherein said hard mask layer comprises silicon oxynitride. 
     
     
       11. The method according to  claim 9  wherein said step of etching said resist mask to trim said resist mask comprises a chemistry containing O 2  gas. 
     
     
       12. The method according to  claim 9  wherein said step of etching said hard mask layer comprises a chemistry of CF 4  gas. 
     
     
       13. The method according to  claim 9  wherein said step of stripping away said resist layer comprises a chemistry containing O 2  gas. 
     
     
       14. The method according to  claim 9  wherein said step of etching said polysilicon layer comprises a main etch step followed by an overetch step. 
     
     
       15. The method according to  claim 9  wherein said step of etching said polysilicon layer comprises a chemistry of: HBr gas, Cl 2  gas, He—O 2  gas, and combinations thereof. 
     
     
       16. A method to pattern a polysilicon layer in the manufacture of an integrated circuit device comprising:
 providing a gate oxide overlying a semiconductor substrate;  
 providing a polysilicon layer overlying said gate oxide layer;  
 providing a silicon oxynitride layer overlying said polysilicon layer;  
 providing a silicon dioxide layer overlying said silicon oxynitride layer;  
 providing a resist layer overlying said silicon dioxide layer;  
 patterning said resist layer to form a resist mask that exposes a part of said silicon dioxide layer;  
 patterning said polysilicon layer wherein said patterning is performed sequentially in a dry plasma etch chamber and wherein said patterning comprises: 
 etching said resist mask to trim said resist mask;  
 thereafter etching said silicon dioxide layer and said silicon oxynitride layer exposed by said resist mask to form a hard mask that exposes a part of said polysilicon layer;  
 thereafter stripping away said resist mask;  
 thereafter cleaning away polymer residue from said resist mask wherein said cleaning away comprises a chemistry containing CF 4  gas; and  
 thereafter etching said polysilicon layer exposed by said hard mask wherein said etching comprises a main etch step followed by an overetch step; and  
 
 stripping away said hard mask to complete the patterning of said polysilicon layer in the manufacture of the integrated circuit device.  
 
     
     
       17. The method according to  claim 16  wherein said step of etching said silicon dioxide layer and said silicon oxynitride layer comprises a chemistry of CF 4  gas. 
     
     
       18. The method according to  claim 16  wherein said step of stripping away said resist layer comprises a chemistry containing O 2  gas. 
     
     
       19. The method according to  claim 16  wherein said step of etching said polysilicon layer comprises a chemistry of: HBr gas, Cl 2  gas, He—O 2  gas, and combinations thereof. 
     
     
       20. A method of forming a semiconductor device, the method comprising:
   providing a semiconductor substrate with a conductive layer formed thereon;        providing a hard mask layer above said conductive layer, said hard mask layer comprising silicon oxynitride;        providing a buffer layer above said hard mask layer;        providing a resist layer above said buffer layer;        patterning said resist layer to form a resist mask that exposes a part of said buffer layer; and        patterning said conductive layer in a dry plasma etch chamber, said patterning comprising:      etching said hard mask layer and said buffer layer exposed by said resist mask to form a hard mask that exposes a part of said conductive layer;        thereafter stripping away said resist mask; and        thereafter etching said conductive layer exposed by said hard mask.       
     
     
       21. The method of  claim 20  wherein said buffer layer comprises an oxide. 
     
     
       22. The method of  claim 20  wherein said buffer layer comprises silicon dioxide. 
     
     
       23. The method of  claim 20  wherein said step of etching said hard mask layer comprises a chemistry containing CF 4    gas.   
     
     
       24. The method of  claim 20  wherein said step of etching said conductive layer comprises a main etch step followed by an overetch step. 
     
     
       25. The method of  claim 20  further comprising etching said resist layer to trim said resist layer prior to said step of etching said hard mask layer wherein said etching of said resist layer is performed in said dry plasma etch chamber. 
     
     
       26. A method for forming a semiconductor device, the method comprising:
   providing a polysilicon layer overlying a semiconductor substrate;        providing a hard mask layer overlying said polysilicon layer;        providing a resist layer overlying said hard mask layer;        patterning said resist layer to form a resist mask that exposes a part of said hard mask layer; and        patterning said polysilicon layer in a dry plasma etch chamber and wherein said patterning comprises:      etching said hard mask layer exposed by said resist mask to form a hard mask that exposes a part of said polysilicon layer;        stripping away said resist mask in a first process step;        removing polymer residue resulting from said stripping step in a second process step; and        etching said polysilicon layer exposed by said hard mask.       
     
     
       27. The method of  claim 26  wherein the step of patterning said polysilicon layer includes stripping away said hard mask. 
     
     
       28. The method of  claim 26  further comprising cleaning away polymer residue from said hard mask after stripping away said resist mask. 
     
     
       29. The method of  claim 26  wherein said hard mask layer comprises silicon oxynitride. 
     
     
       30. The method of  claim 26  wherein the step of etching said hard mask layer comprises a chemistry containing CF 4    gas.   
     
     
       31. The method of  claim 26  wherein said step of etching said polysilicon layer comprises a main etch step followed by an overetch step. 
     
     
       32. The method of  claim 26  further comprising etching said resist layer to trim said resist layer prior to said step of etching said hard mask layer wherein said etching of said resist layer is performed in said dry plasma etch chamber. 
     
     
       33. A method for forming a semiconductor device, the method comprising:
   providing a wafer having a substrate, a first layer formed on the substrate, a hard mask layer formed on the first layer, a buffer layer formed on said hard mask layer, and a resist layer formed on the buffer layer;        patterning said hard mask layer and said buffer layer to form a hard mask that exposes a part of said first layer;        removing said resist layer; and        patterning said first layer by etching said first layer and removing said hard mask layer and said buffer layer.     
     
     
       34. The method of  claim 33  wherein the steps of patterning said hard mask layer, removing said resist layer, and patterning said first layer are performed in a dry plasma etch chamber. 
     
     
       35. The method of  claim 33  wherein the step of patterning said hard mask layer includes etching the hard mask layer and the buffer layer. 
     
     
       36. The method of  claim 35  wherein said step of etching said hard mask layer comprises a chemistry containing CF 4    gas.   
     
     
       37. The method of  claim 33  wherein said step of etching said first layer comprises a main etch step followed by an overetch step. 
     
     
       38. The method of  claim 33  wherein the step of patterning said hard mask layer includes patterning a resist layer. 
     
     
       39. The method of  claim 38  further comprising etching said resist layer to trim said resist layer prior to said step of etching said hard mask layer wherein said etching of said resist layer is performed in said dry plasma etch chamber. 
     
     
       40. The method of  claim 33  wherein said hard mask layer comprises silicon oxynitride. 
     
     
       41. The method of  claim 33  wherein said buffer layer comprises an oxide. 
     
     
       42. The method of  claim 33  wherein said buffer layer comprises silicon dioxide. 
     
     
       43. A method of forming a semiconductor device, the method comprising:
   providing a semiconductor substrate with a conductive layer formed thereon;        providing a hard mask layer above said conductive layer;        providing a resist layer above said hard mask layer;        patterning said resist layer to form a resist mask that exposes a part of said hard mask layer; and        patterning said conductive layer in a dry plasma etch chamber, said patterning comprising:      etching said hard mask layer exposed by said resist mask to form a hard mask that exposes a part of said conductive layer;        thereafter stripping away said resist mask using a first chemistry;        thereafter removing polymer residue using a second chemistry different from the first chemistry; and        thereafter etching said conductive layer exposed by said hard mask.       
     
     
       44. The method of  claim 43  wherein said hard mask layer comprises silicon oxynitride. 
     
     
       45. The method of  claim 43  wherein said step of etching said hard mask layer comprises a chemistry containing CF 4    gas.   
     
     
       46. The method of  claim 43  wherein said step of etching said conductive layer comprises a main etch step followed by an overetch step. 
     
     
       47. The method of  claim 43  further comprising etching said resist layer to trim said resist layer prior to said step of etching said hard mask layer wherein said etching of said resist layer is performed in said dry plasma etch chamber. 
     
     
       48. A method for forming a semiconductor device, the method comprising:
   providing a wafer having a substrate, a first layer formed on the substrate, a hard mask layer formed on the first layer, a buffer layer formed on said hard mask layer, and a resist layer formed on the buffer layer;        patterning said hard mask layer to form a hard mask that exposes a part of said first layer;        removing said resist layer; and        patterning said first layer by etching said first layer and removing said hard mask layer.     
     
     
       49. The method of  claim 48  wherein the steps of patterning said hard mask layer, removing said resist layer, and patterning said first layer are performed in a dry plasma etch chamber. 
     
     
       50. The method of  claim 48  wherein the step of patterning said hard mask layer includes etching the hard mask layer. 
     
     
       51. The method of  claim 50  wherein said step of etching said hard mask layer comprises a chemistry containing CF 4    gas.   
     
     
       52. The method of  claim 48  wherein said step of etching said first layer comprises a main etch step followed by an overetch step. 
     
     
       53. The method of  claim 48  wherein the step of patterning said hard mask layer includes patterning a resist layer. 
     
     
       54. The method of  claim 53  further comprising etching said resist layer to trim said resist layer prior to said step of etching said hard mask layer wherein said etching of said resist layer is performed in said dry plasma etch chamber. 
     
     
       55. The method of  claim 48  wherein said hard mask layer comprises silicon oxynitride.