Methods of packaging an integrated circuit and methods of forming an integrated circuit package

Abstract

The present invention includes an integrated circuit package, a ball-grid array integrated circuit package, a method of packaging an integrated circuit, and a method of forming an integrated circuit package. According to one aspect, the present invention provides an integrated circuit package including a substrate including a first surface, a second surface and a plurality of conductors, the first surface includes a plurality of conductive pads adapted to couple with a plurality of corresponding bond pads of a semiconductor die, and the conductors being configured to couple the conductive pads with the second surface; and a plurality of conductive bumps coupled with the second surface of the substrate and electrically coupled with respective conductors, the conductive bumps being formed in an array including a plurality of power bumps and signal bumps, and the signal bumps being individually positioned immediately adjacent at least one power bump. One method of packaging an integrated circuit includes providing a semiconductor die including a plurality of bond pads; providing a package substrate including a plurality of conductive bumps including plural power bumps and plural signal bumps; arranging individual signal bumps to be immediately adjacent at least one power bump; and electrically coupling the bond pads of the semiconductor die with respective conductive bumps.

1. A method of packaging an integrated circuit comprising:
 providing a semiconductor die including a plurality of bond pads; 
 providing a package substrate including a plurality of conductive bumps including plural power bumps and plural signal bumps; 
 arranging individual signal bumps to be immediately adjacent at least one power bump; and 
 electrically coupling the bond pads of the semiconductor die with respective conductive bumps. 
 
     
     
       2. The method according to  claim 1  further comprising:
 providing an external substrate having a plurality of conductive pads; and 
 electrically coupling the conductive bumps with respective conductive pads of the external substrate. 
 
     
     
       3. The method according to  claim 1  wherein the providing the package substrate comprises providing a package substrate including conductive bumps formed as balls of a ball-grid array integrated circuit package. 
     
     
       4. The method according to  claim 1  further comprising:
 forming plural vias within the package substrate; and 
 providing conductors within the vias. 
 
     
     
       5. A method of packaging an integrated circuit comprising:
 providing a semiconductor die including a plurality of pads;   providing a package substrate including a plurality of conductive bumps arranged in an array including plural power bumps and plural signal bumps;   arranging plural sides of the array to individually include at least a majority of signal bumps; and   electrically coupling the pads of the semiconductor die with respective conductive bumps.   
     
     
       6. The method according to  claim 5  further comprising A method of packaging an integrated circuit comprising:
 providing a semiconductor die including a plurality of pads; 
 providing a package substrate including a plurality of conductive bumps arranged in an array including plural power bumps and plural signal bumps; 
 arranging plural sides of the array to individually include at least a majority of signal bumps; 
 electrically coupling the pads of the semiconductor die with respective conductive bumps; and 
 arranging individual signal bumps to be immediately adjacent at least one power bump. 
 
     
     
       7. The method according to  claim 5  claim 6 further comprising:
 providing an external substrate having a plurality of conductive pads; and 
 electrically coupling the conductive bumps with respective conductive pads of the external substrate. 
 
     
     
       8. The method according to  claim 5  claim 6 wherein the providing the package substrate comprises providing a package substrate including conductive bumps formed as balls of a ball-grid array integrated circuit package. 
     
     
       9. The method according to  claim 5  claim 6 further comprising:
 forming plural vias within the package substrate; and 
 providing via conductors within the vias. 
 
     
     
       10. A method of forming an integrated circuit package comprising:
 providing a package substrate including a plurality of conductive bumps including plural power bumps and plural signal bumps; and 
 arranging individual signal bumps to be immediately adjacent at least one power bump. 
 
     
     
       11. The method according to  claim 10  further comprising providing a plurality of conductive pads configured to couple with the a plurality of bond pads of an integrated circuit and the power bumps and the signal bumps. 
     
     
       12. The method according to  claim 10  wherein the providing the package substrate comprises providing the package substrate including conductive bumps formed as balls of a ball-grid array integrated circuit package. 
     
     
       13. A method of packaging an integrated circuit comprising:
 providing a package substrate including a plurality of conductive bumps arranged in an array including plural power bumps and plural signal bumps; and   arranging plural sides of the array to individually include a majority of signal bumps.   
     
     
       14. The method according to  claim 13  further comprising A method of packaging an integrated circuit comprising:
 providing a package substrate including a plurality of conductive bumps arranged in an array including plural power bumps and plural signal bumps; 
 arranging plural sides of the array to individually include a majority of signal bumps; and 
 arranging individual signal bumps to be immediately adjacent at least one power bump. 
 
     
     
       15. The method according to  claim 13  claim 14 further comprising providing a plurality of conductive pads configured to couple with the a plurality of bond pads of an integrated circuit and the power bumps and the signal bumps. 
     
     
       16. The method according to  claim 13  claim 14 wherein the providing the package substrate comprises providing a package substrate including conductive bumps formed as balls of a ball-grid array integrated circuit package. 
     
     
       17. A method of packaging an integrated circuit comprising:
 providing a semiconductor die including a plurality of pads;   providing a package substrate including a plurality of conductive bumps arranged in an array including plural power bumps and plural signal bumps;   arranging plural sides of the array to individually include at least a majority of signal bumps;   arranging plural rows or columns of the array to individually include at least a majority of power bumps; and   electrically coupling the pads of the semiconductor die with respective conductive bumps.   
     
     
       18. The method according to claim 17 wherein the plural rows or columns of the array are individually adjacent to respective ones of the plural sides of the array. 
     
     
       19. The method according to claim 18 further comprising arranging each of the majority of signal bumps in the plural sides of the array to be immediately adjacent at least one of the plural power bumps. 
     
     
       20. The method according to claim 17 wherein the plurality of conductive bumps arranged in an array include a center array substantially spaced apart from a periphery array. 
     
     
       21. The method according to claim 20 wherein the center array includes a majority of power bumps. 
     
     
       22. The method according to claim 17 wherein the plural power bumps comprise Vss or Vdd bumps. 
     
     
       23. The method according to claim 17 further comprising arranging each of the majority of signal bumps in the plural sides of the array to be immediately adjacent at least one of the plural power bumps. 
     
     
       24. The method according to claim 17 further comprising arranging a plural of corner bumps diagonally arranged intermediate adjacent sides of the array. 
     
     
       25. The method according to claim 17 further comprising:
 providing an external substrate having a plurality of conductive pads; and   electrically coupling the conductive bumps with respective conductive pads of the external substrate.   
     
     
       26. The method according to claim 17 wherein the providing the package substrate comprises providing a package substrate including conductive bumps formed as balls of a ball-grid array integrated circuit package. 
     
     
       27. The method according to claim 17 further comprising:
 forming plural vias within the package substrate; and   providing conductors within the vias.   
     
     
       28. A method of packaging an integrated circuit comprising:
 providing a package substrate including a plurality of conductive bumps arranged in an array including plural power bumps and plural signal bumps;   arranging plural sides of the array to individually include a majority of signal bumps; and   arranging plural rows or columns of the array to individually include at least a majority of power bumps.   
     
     
       29. The method according to claim 28 wherein the plural rows or columns of the array are individually adjacent to the plural sides of the array. 
     
     
       30. The method according to claim 28 wherein the plurality of conductive bumps arranged in an array include a center array substantially spaced apart from a periphery array. 
     
     
       31. The method according to claim 30 wherein the center array includes a majority of power bumps. 
     
     
       32. The method according to claim 29 further comprising arranging individual ones of the majority of signal bumps in the plural sides of the array to be immediately adjacent at least one of the majority of power bumps of the plural rows or columns of the array. 
     
     
       33. The method according to claim 28 wherein the plural power bumps comprise Vss or Vdd bumps. 
     
     
       34. The method according to claim 28 further comprising arranging individual ones of the majority of signal bumps in the plural sides of the array to be immediately adjacent at least one of the plural power bumps. 
     
     
       35. The method according to claim 28 further comprising:
 providing an external substrate having a plurality of conductive pads; and   electrically coupling the conductive bumps with respective conductive pads of the external substrate.   
     
     
       36. The method according to claim 28 further comprising arranging a plurality of corner bumps diagonally arranged intermediate adjacent sides of the array. 
     
     
       37. The method according to claim 28 wherein the providing the package substrate comprises providing a package substrate including conductive bumps formed as balls of a ball-grid array integrated circuit package. 
     
     
       38. The method according to claim 28 further comprising:
 forming plural vias within the package substrate; and   providing conductors within the vias.