Semiconductor device having deep trench charge compensation regions and method

Abstract

In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.

We claim: 
     
       1. A semiconductor device comprising:
 a body of semiconductor material; and 
 a charge compensation region including a trench formed in the body of semiconductor material, wherein the trench comprises a pair of opposite conductivity type single crystal semiconductor layers overlying surfaces of the trench, and wherein a first intrinsic layer separates the pair, and wherein a passivation liner is formed overlying an outermost one of the pair. 
 
     
     
       2. The device of  claim 1 , wherein the passivation liner comprises an oxide. 
     
     
       3. The device of  claim 1  further comprising a conductive layer coupled to the charge compensation region. 
     
     
       4. The device of  claim 1 , wherein the passivation liner comprises a dielectric material. 
     
     
       5. The device of  claim 1 , wherein the passivation liner comprises a nitride. 
     
     
       6. The device of  claim 1 , wherein the passivation liner comprises an oxide and a nitride. 
     
     
       7. The device of  claim 1 , wherein the charge compensation region further includes a void. 
     
     
       8. The device of  claim 7 , wherein the void is formed at a centralized portion of the charge compensation region. 
     
     
       9. A semiconductor device comprising:
 a body of semiconductor material; and 
 a trench formed in the body of semiconductor material; 
 a first layer comprising a single crystal semiconductor material formed overlying surfaces of the trench, wherein the first layer comprises a first conductivity type; 
 a first intrinsic layer formed overlying the first layer; 
 a second layer comprising a single crystal semiconductor material formed overlying the first intrinsic layer, wherein the second layer comprises a second conductivity type, and wherein the first intrinsic layer is configured to reduce intermixing of dopants between the first and second layers; and 
 a passivation layer formed overlying the second layer to form a charge compensation region. 
 
     
     
       10. The device of  claim 9  further comprising a conductive layer coupled to the charge compensation region. 
     
     
       11. The device of  claim 9 , wherein the trench includes a void. 
     
     
       12. The device of  claim 9 , wherein the passivation layer comprises a dry oxide layer. 
     
     
       13. A semiconductor device comprising:
 a body of semiconductor material having first and second opposing major surfaces; 
 a trench formed in the body of semiconductor material; 
 a first semiconductor layer of a first conductivity type formed adjoining surfaces of the trench; 
 a first intrinsic layer formed adjoining the first semiconductor layer; 
 a second semiconductor layer of a second conductivity type formed adjacent to the first intrinsic to form a charge compensated region; 
 a passivation layer formed overlying the second semiconductor layer; 
 a first doped region in the body of semiconductor material formed adjacent the charge compensated region, wherein the first doped region comprises the second conductivity type; 
 a second doped region formed in the first doped region and comprising the first conductivity type; and 
 a control electrode formed adjacent the first and second doped regions. 
 
     
     
       14. The device of  claim 13  further comprising a conductive layer coupled to the charge compensated region. 
     
     
       15. The device of  claim 13 , wherein the control electrode comprises a spacer gate structure. 
     
     
       16. The device of  claim 13 , wherein the passivation layer comprises an oxide layer. 
     
     
       17. The device of  claim 13 , wherein the passivation layer comprises a nitride layer. 
     
     
       18. The device of  claim 13 , wherein the passivation layer comprises an oxide layer and a nitride layer. 
     
     
       19. The device of  claim 13 , wherein the charge compensated region has a void. 
     
     
       20. A semiconductor device comprising:
 a substrate of a first conductivity type;   a semiconductor layer overlying the substrate, wherein the semiconductor layer has a major surface spaced apart from the substrate;   a vertically-oriented conductive region of the first conductivity type adjacent the major surface and extending towards the substrate;   a horizontally-oriented doped region of the first conductivity type adjacent to the major surface;   a body region of a second conductivity type adjacent to another portion of the major surface, wherein the horizontally-oriented doped region adjoins the body region and the vertically-oriented conductive region;   a conductive layer configured to reduce gate to drain capacitance; and   a gate electrode spaced apart from and electrically insulated from the body region and the horizontally-oriented doped region.   
     
     
       21. The device of claim 20 further comprising a source region of the first conductivity type in the body region, wherein source region is electrically connected to the conductive electrode. 
     
     
       22. The device of claim 20, wherein the vertically-oriented conductive region comprises a doped semiconductor layer. 
     
     
       23. The device of claim 20, further comprising a doped region of the second conductivity type below the horizontally-oriented doped region and within the semiconductor layer. 
     
     
       24. The device of claim 23, wherein the doped region is adjacent the body region. 
     
     
       25. The device of claim 23, wherein the doped region adjoins the horizontally-oriented doped region. 
     
     
       26. The device of claim 23, wherein the doped region adjoins the body region and the horizontally-oriented doped region. 
     
     
       27. The device of claim 23, wherein the doped region adjoins the vertically-oriented conductive region. 
     
     
       28. The device of claim 23, wherein the doped region is spaced apart from the substrate. 
     
     
       29. A semiconductor device structure comprising:
 a body of semiconductor material including a substrate of a first conductivity type and a semiconductor layer in spaced relationship with the substrate and having a major surface;   a body region of a second conductivity type adjacent the major surface;   a first conductive layer of the first conductivity type adjacent the major surface and extending vertically towards the substrate, wherein the first conductive layer is spaced apart from the body region and configured to provide a vertical current path for the semiconductor device;   a second conductive layer of the first conductivity type adjacent the major surface and laterally adjoining the body region and the first conductive layer, wherein the second conductive layer is configured as a low resistance horizontal current path for the semiconductor device; and   an insulated gate electrode adjacent the body region and the second conductive layer.   
     
     
       30. The structure of claim 29, wherein the first conductive layer comprises a doped semiconductor layer. 
     
     
       31. The structure of claim 29 further comprising a conductive electrode overlying the first conductive layer. 
     
     
       32. The structure of claim 31 further comprising a source region in the body region, wherein the source region is electrically coupled to the conductive electrode. 
     
     
       33. The structure of claim 29, further comprising a doped region of the second conductivity type below the second conductive layer. 
     
     
       34. The structure of claim 33, wherein the doped region is adjacent the body region. 
     
     
       35. The structure of claim 33, wherein the doped region adjoins the second conductive layer. 
     
     
       36. The structure of claim 33, wherein the doped region adjoins the body region and the second conductive layer. 
     
     
       37. The structure of claim 33, wherein the doped region adjoins the first conductive layer. 
     
     
       38. The structure of claim 33, wherein the doped region is spaced apart from the semiconductor substrate. 
     
     
       39. The structure of claim 29 further comprising a conductive electrode overlying the second conductive layer. 
     
     
       40. A semiconductor device structure comprising:
 a body of semiconductor material including a substrate of a first conductivity type and a semiconductor layer in spaced relationship with the substrate and having a major surface;   a body region of a second conductivity type adjacent the major surface;   a first conductive layer of the first conductivity type adjacent the major surface and extending vertically towards the substrate, wherein the first conductive layer is spaced apart from the body region and configured to provide a vertical current path for the semiconductor device;   a doped region of the first conductivity type adjacent the major surface and horizontally adjoining the body region and the first conductive layer, wherein the doped region is configured as a low resistance horizontal current path for the semiconductor device; and   an insulated gate electrode adjacent the body region and the doped region.