Masks formed based on integrated circuit layout design having cell that includes extended active region

Abstract

A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.

What is claimed is: 
     
       1. A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
 a first cell comprising a first transistor region and a second transistor region; 
 a second cell comprising a third transistor region and a fourth transistor region, 
 wherein 
 the first cell and the second cell adjoin each other at side cell boundaries thereof, 
 the first transistor region and the third transistor region are formed in a first continuous active region, and 
 the second transistor region and the fourth transistor region are formed in a second continuous active region; and 
 a middle gate strip electrically continuously extending from the first transistor region to the second transistor region, along a line at which the first cell adjoins the second cell, 
 wherein the set of masks is formed based on the integrated circuit layout. 
 
     
     
       2. The set of masks of  claim 1 , wherein the first cell further comprises:
 a first gate strip; and 
 upper and lower cell boundaries on opposite ends of the first cell, 
 wherein 
 the side cell boundaries are parallel to the first gate strip; 
 the first transistor region comprises a first PMOS transistor comprising a first portion of the first gate strip as a first gate, a first source region and a first drain region adjacent to the first gate, and 
 the second transistor region comprises a first NMOS transistor comprising a second portion of the first gate strip as a second gate, and a second source region and a second drain region adjacent to the second gate. 
 
     
     
       3. The set of masks of  claim 2 , wherein the second cell further comprises:
 a second gate strip parallel to the first gate strip; and 
 upper and lower cell boundaries on opposite sides of the second cell, 
 wherein 
 the third transistor region comprises a second PMOS transistor comprising a first portion of the second gate strip as a third gate, and a third source region and a third drain region adjacent to the third gate, and 
 the fourth transistor region comprises a second NMOS transistor comprising a second portion of the second gate strip as a fourth gate, and a fourth source region and a fourth drain region adjacent to the fourth gate. 
 
     
     
       4. The set of masks of  claim 3 , wherein the first gate strip and is an active gate strip, the second gate strips are strip is an active gate strips strip and the middle gate strip is a dummy gate strip. 
     
     
       5. The set of masks of  claim 3 , wherein the integrated circuit layout further comprises:
 a first power supply line extending across the upper cell boundaries of the first cell and the second cell; and 
 a second power supply line extending across the lower cell boundaries of the first cell and the second cell, 
 wherein the first power supply line is electrically coupled to the first source region and the third source region and the second power supply line is electrically coupled to the second source region and the fourth source region. 
 
     
     
       6. The set of masks of  claim 5 , wherein:
 an upper portion of the middle gate strip, the first drain region, and the third source region form a parasitic transistor;   a lower portion of the middle gate strip, the second drain region, and the fourth source region form a parasitic transistor;   the upper portion of the middle gate strip is electrically coupled to the first power supply line; and   the lower portion of the middle gate strip is electrically coupled to the second power supply line.   
     
     
       7. The set of masks of  claim 1 , wherein:
 the first cell further comprises a first dummy gate strip along the side cell boundary opposite to the middle gate strip and the second cell further comprises a second dummy gate strip along the side cell boundary opposite to the middle gate strip. 
 
     
     
       8. The set of masks of  claim 1 , wherein:
 the first continuous active region extends to the side cell boundaries of the first cell, and the second continuous active region extends to the side cell boundaries of the second cell. 
 
     
     
       9. A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
 a first cell comprising a first active region and a first side boundary; 
 a second cell comprising a second active region and a second side boundary along the first side boundary; 
 a first gate strip in the first cell parallel to the first side boundary and overlying the first active region; 
 a second gate strip in the second cell parallel to the second side boundary and overlying the second active region; and 
 a dummy gate strip parallel to and between the first gate strip and the second gate strip, 
 wherein the dummy gate strip overlies one of the first active region or and the second active region, and the dummy gate strip is electrically continuous, 
 wherein the set of masks is formed based on the integrated circuit layout. 
 
     
     
       10. The set of masks of  claim 9 , wherein:
 the first cell further comprises a third active region, 
 the second cell further comprises a fourth active region, 
 when the dummy gate strip overlies the first active region, the dummy gate strip also overlies the third active region, and 
 when the dummy gate strip overlies the second active region, the dummy gate strip also overlies the fourth active region. 
 
     
     
       11. The set of masks of  claim 9 , wherein the integrated circuit layout further comprises a first power supply line along a direction perpendicular to the dummy gate strip, wherein the first active region comprises a first source region electrically coupled to the first power supply line. 
     
     
       12. The set of masks of  claim 11 , wherein the integrated circuit layout further comprises a second power supply line along the direction perpendicular to the dummy gate strip, wherein the second active region comprises a second source region electrically coupled to the second power supply line. 
     
     
       13. The set of masks of  claim 12 , wherein the first power supply line is electrically coupled to the second power supply line. 
     
     
       14. The set of masks of  claim 12 , wherein the first power supply line is electrically separate from the second power supply line. 
     
     
       15. A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
 a first cell comprising a first active region and a first side boundary; 
 a second cell comprising a second active region and a second side boundary along the first side boundary; 
 a first gate strip in the first cell parallel to the first side boundary and overlying the first active region; 
 a second gate strip in the second cell parallel to the second side boundary and overlying the second active region; 
 a blank region abutting the first active region and the second active region; 
 a first dummy gate strip in the first cell between the first gate strip and the first side boundary, and overlying the first active region and the blank region; and 
 a second dummy gate strip in the second cell between the second gate strip and the second side boundary, and overlying the second active region and the blank region, wherein the second dummy gate strip is electrically continuous with the first dummy gate strip, 
 wherein the set of masks is formed based on the integrated circuit layout. 
 
     
     
       16. The set of masks of  claim 15 , wherein the first dummy gate strip overlies a border between the first active region and the blank region. 
     
     
       17. The set of masks of  claim 15 , wherein:
 the first cell further comprises a third active region, 
 the second cell further comprises a fourth active region, 
 the first dummy gate strip overlies the third active region, and 
 the second dummy gate strip overlies the fourth active region. 
 
     
     
       18. The set of masks of  claim 17 , wherein:
 the first dummy gate strip overlies a first edge of the blank region, and 
 the first active region and the third active region abut the first edge of the blank region. 
 
     
     
       19. The set of masks of  claim 18 , wherein:
 the second dummy gate strip overlies a second edge of the blank region, and 
 the second active region and the fourth active region abut the second edge of the blank region. 
 
     
     
       20. The set of masks of  claim 15 , wherein the second side boundary is along the first side boundary in the blank region. 
     
     
       21. A device, the device comprising:
 a first cell comprising a first transistor region and a second transistor region;   a second cell comprising a third transistor region and a fourth transistor region,   wherein   the first cell and the second cell adjoin each other at side cell boundaries thereof,   the first transistor region and the third transistor region are formed in a first continuous active region, and   the second transistor region and the fourth transistor region are formed in a second continuous active region; and   a middle gate strip electrically continuously extending from the first transistor region to the second transistor region, along a line at which the first cell adjoins the second cell.   
     
     
       22. The device of claim 21, wherein the first cell further comprises:
 a first gate strip; and   upper and lower cell boundaries on opposite ends of the first cell,   wherein   the side cell boundaries are parallel to the first gate strip;   the first transistor region comprises a first PMOS transistor comprising a first portion of the first gate strip as a first gate, a first source region and a first drain region adjacent to the first gate, and   the second transistor region comprises a first NMOS transistor comprising a second portion of the first gate strip as a second gate, and a second source region and a second drain region adjacent to the second gate.   
     
     
       23. The device of claim 22, wherein the second cell further comprises:
 a second gate strip parallel to the first gate strip; and   upper and lower cell boundaries on opposite sides of the second cell,   wherein   the third transistor region comprises a second PMOS transistor comprising a first portion of the second gate strip as a third gate, and a third source region and a third drain region adjacent to the third gate, and   the fourth transistor region comprises a second NMOS transistor comprising a second portion of the second gate strip as a fourth gate, and a fourth source region and a fourth drain region adjacent to the fourth gate.   
     
     
       24. The device of claim 23, wherein the first gate strip and the second gate strip are active gate strips and the middle gate strip is a dummy gate strip. 
     
     
       25. The device of claim 23, wherein the device further comprises:
 a first power supply line extending across the upper cell boundaries of the first cell and the second cell; and   a second power supply line extending across the lower cell boundaries of the first cell and the second cell,   wherein the first power supply line is electrically coupled to the first source region and the third source region and the second power supply line is electrically coupled to the second source region and the fourth source region.   
     
     
       26. The device of claim 21, wherein:
 the first cell further comprises a first dummy gate strip along the side cell boundary opposite to the middle gate strip and the second cell further comprises a second dummy gate strip along the side cell boundary opposite to the middle gate strip.   
     
     
       27. The device of claim 21, wherein:
 the first continuous active region extends to the side cell boundaries of the first cell, and   the second continuous active region extends to the side cell boundaries of the second cell.   
     
     
       28. A device, the device comprising:
 a first cell comprising a first active region and a first side boundary;   a second cell comprising a second active region and a second side boundary along the first side boundary;   a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;   a second gate strip in the second cell parallel to the second side boundary and overlying the second active region; and   a dummy gate strip parallel to and between the first gate strip and the second gate strip,   wherein the dummy gate strip is electrically continuous and overlies the first active region and the second active region.   
     
     
       29. The device of claim 28, wherein:
 the first cell further comprises a third active region,   the second cell further comprises a fourth active region.   
     
     
       30. The device of claim 28, wherein the device further comprises a first power supply line along a direction perpendicular to the dummy gate strip, wherein the first active region comprises a first source region electrically coupled to the first power supply line. 
     
     
       31. The device of claim 30, wherein the device further comprises a second power supply line along the direction perpendicular to the dummy gate strip, wherein the second active region comprises a second source region electrically coupled to the second power supply line. 
     
     
       32. The device of claim 28, wherein the first power supply line is electrically coupled to the second power supply line. 
     
     
       33. The device of claim 28, wherein the first power supply line is separate from the second power supply line. 
     
     
       34. A device, the device comprising:
 a first cell comprising a first active region and a first side boundary;   a second cell comprising a second active region and a second side boundary along the first side boundary;   a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;   a second gate strip in the second cell parallel to the second side boundary and overlying the second active region;   a blank region abutting the first active region and the second active region;   a first dummy gate strip between the first gate strip and the first side boundary, and overlying the first active region and the blank region; and   a second dummy gate strip overlying the second active region and the blank region, wherein the second dummy gate strip is electrically continuous with the first dummy gate strip.   
     
     
       35. The device of claim 34, wherein the first dummy gate strip overlies a border between the first active region and the blank region. 
     
     
       36. The device of claim 34, wherein:
 the first cell further comprises a third active region,   the second cell further comprises a fourth active region.   
     
     
       37. The device of claim 36, wherein:
 the first dummy gate strip overlies a first edge of the blank region, and   the first active region and the third active region abut the first edge of the blank region.   
     
     
       38. The device of claim 37, wherein:
 the second dummy gate strip overlies a second edge of the blank region, and   the second active region and the fourth active region abut the second edge of the blank region.   
     
     
       39. The device of claim 34, wherein the second side boundary is along the first side boundary in the blank region.