Inventor · disambiguated record
Dale W. Martin
Also filed as: MARTIN DALE · MARTIN DALE W · MARTIN DALE WARNER
23 granted patents·3 pending applications·690 citations·filing 1987–2014
96Inventor score
Top patents by PatentIndex Score
26 records- 0196US6610607B1Method to define and tailor process limited lithographic features using a modified hard mask processIBM·Filed 2000·Granted Aug 26, 2003·217 cites·22 claims
- 0293US7883990B2High resistivity SOI base wafer using thermally annealed substrateIBM·Filed 2007·Granted Feb 8, 2011·29 cites·7 claims
- 0393US5972765AUse of deuterated materials in semiconductor processingIBM·Filed 1997·Granted Oct 26, 1999·140 cites·35 claims
- 0491US9355936B2Flattened substrate surface for substrate bondingGLOBALFOUNDRIES INC·Filed 2014·Granted May 31, 2016·16 cites·20 claims
- 0591US6525371B2Self-aligned non-volatile random access memory cell and process to make the sameIBM·Filed 1999·Granted Feb 25, 2003·98 cites·19 claims
- 0686US6258673B1Multiple thickness of gate oxideIBM·Filed 1999·Granted Jul 10, 2001·69 cites·30 claims
- 0781US8951896B2High linearity SOI wafer for low-distortion circuit applicationsIBM·Filed 2013·Granted Feb 10, 2015·4 cites·20 claims
- 0878US8778737B2Flattened substrate surface for substrate bondingCOONEY III EDWARD C·Filed 2011·Granted Jul 15, 2014·4 cites·22 claims
- 0972US7446007B2Multi-layer spacer with inhibited recess/undercut and method for fabrication thereofIBM·Filed 2006·Granted Nov 4, 2008·5 cites·13 claims
- 1072US7190007B2Isolated fully depleted silicon-on-insulator regions by selective etchIBM·Filed 2004·Granted Mar 13, 2007·15 cites·17 claims
- 1167US9165819B2High linearity SOI wafer for low-distortion circuit applicationsIBM·Filed 2014·Granted Oct 20, 2015·1 cites·20 claims
- 1267US6486510B2Reduction of reverse short channel effects by implantation of neutral dopantsIBM·Filed 2001·Granted Nov 26, 2002·9 cites·13 claims
- 1366US6352912B1Reduction of reverse short channel effects by deep implantation of neutral dopantsIBM·Filed 2000·Granted Mar 5, 2002·8 cites·25 claims
- 1464US8679863B2Fine tuning highly resistive substrate resistivity and structures thereofGAMBINO JEFFREY P·Filed 2012·Granted Mar 25, 2014·1 cites·22 claims
- 1561US7303952B2Method for fabricating doped polysilicon linesIBM·Filed 2004·Granted Dec 4, 2007·8 cites·19 claims
- 1659US6949458B2Self-aligned contact areas for sidewall image transfer formed conductorsIBM·Filed 2003·Granted Sep 27, 2005·7 cites·20 claims
- 1755US6197632B1Method for dual sidewall oxidation in high density, high performance DRAMSIBM·Filed 1999·Granted Mar 6, 2001·14 cites·12 claims
- 1854US7157341B2Gate stacksIBM·Filed 2004·Granted Jan 2, 2007·5 cites·16 claims
- 1950US6294429B1Method of forming a point on a floating gate for electron injectionIBM·Filed 1999·Granted Sep 25, 2001·12 cites·32 claims
- 2049US6566759B1Self-aligned contact areas for sidewall image transfer formed conductorsIBM·Filed 1999·Granted May 20, 2003·12 cites·19 claims
- 2149USD307153SViewer for a doorREJAN INC·Filed 1987·Granted Apr 10, 1990·6 cites·1 claims
- 2249US2007128776A1Isolated fully depleted silicon-on-insulator regions by selective etchIBM·Filed 2007·Application pending·0 cites
- 2347US5926708AMethod for providing multiple gate oxide thicknesses on the same waferIBM·Filed 1997·Granted Jul 20, 1999·10 cites·6 claims
- 2447US2007287275A1Method for fabricating doped polysilicon linesADKISSON JAMES W·Filed 2007·Application pending·0 cites
- 2546US7378712B2Gate stacksIBM·Filed 2006·Granted May 27, 2008·0 cites·7 claims
- 2638US2006163670A1Dual silicide process to improve device performanceIBM·Filed 2005·Application pending·0 cites
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