Inventor · disambiguated record
Johannes M. Van Meer
Also filed as: VAN MEER JOHANNES · VAN MEER JOHANNES M · VAN MEER JOHANNES MARINUS
37 granted patents·10 pending applications·101 citations·filing 2005–2024
96Inventor score
Files withAPPLIED MATERIALS INC21GLOBALFOUNDRIES INC14VARIAN SEMICONDUCTOR EQUIPMENT ASS INC9ADVANCED MICRO DEVICES INC2PEI GEN1
Top patents by PatentIndex Score
47 records- 0195US9082698B1Methods to improve FinFet semiconductor device behavior using co-implantation under the channel regionGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 14, 2015·30 cites·21 claims
- 0293US11942361B2Semiconductor device cavity formation using directional depositionAPPLIED MATERIALS INC·Filed 2021·Granted Mar 26, 2024·2 cites·15 claims
- 0393US10403552B1Replacement gate formation with angled etch and depositionVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2018·Granted Sep 3, 2019·7 cites·20 claims
- 0491US7329599B1Method for fabricating a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2005·Granted Feb 12, 2008·20 cites·18 claims
- 0590US11205593B2Asymmetric fin trimming for fins of FinFET deviceAPPLIED MATERIALS INC·Filed 2020·Granted Dec 21, 2021·2 cites·14 claims
- 0689US10685865B2Method and device for power rail in a fin type field effect transistorVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2018·Granted Jun 16, 2020·5 cites·18 claims
- 0785US10629741B1Method and device for shallow trench isolation in a fin type field effect transistorsAPPLIED MATERIALS INC·Filed 2018·Granted Apr 21, 2020·4 cites·7 claims
- 0884US7442601B2Stress enhanced CMOS circuits and methods for their fabricationADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 28, 2008·10 cites·18 claims
- 0978US9437740B2Epitaxially forming a set of fins in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 6, 2016·2 cites·7 claims
- 1078US7745296B2Raised source and drain process with disposable spacersGLOBALFOUNDRIES INC·Filed 2005·Granted Jun 29, 2010·7 cites·13 claims
- 1177US10090166B2Techniques for forming isolation structures in a substrateVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2017·Granted Oct 2, 2018·2 cites·18 claims
- 1275US10510610B2Structure and method of forming fin device having improved fin linerVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2018·Granted Dec 17, 2019·1 cites·16 claims
- 1372US9812336B2FinFET semiconductor structures and methods of fabricating sameGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 7, 2017·2 cites·3 claims
- 1469US8962441B2Transistor device with improved source/drain junction architecture and methods of making such a deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 24, 2015·2 cites·20 claims
- 1568US10269663B2Critical dimensions variance compensationVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2017·Granted Apr 23, 2019·1 cites·9 claims
- 1667US9136330B2Shallow trench isolationGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 15, 2015·1 cites·8 claims
- 1766US9034737B2Epitaxially forming a set of fins in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2013·Granted May 19, 2015·1 cites·20 claims
- 1865US12369299B2Devices and methods for DRAM leakage reductionAPPLIED MATERIALS INC·Filed 2022·Granted Jul 22, 2025·0 cites·15 claims
- 1963US10971403B2Structure and method of forming fin device having improved fin linerVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2019·Granted Apr 6, 2021·0 cites·14 claims
- 2062US12230691B2Three dimensional device formation using early removal of sacrificial heterostructure layerAPPLIED MATERIALS INC·Filed 2022·Granted Feb 18, 2025·0 cites·20 claims
- 2162US11217491B2Replacement gate formation with angled etch and depositionVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2019·Granted Jan 4, 2022·0 cites·20 claims
- 2261US12096622B2Directional etch for improved dual deck three-dimensional NAND architecture marginAPPLIED MATERIALS INC·Filed 2021·Granted Sep 17, 2024·0 cites·10 claims
- 2360US12300494B2Ion implantation process to form punch through stopperAPPLIED MATERIALS INC·Filed 2021·Granted May 13, 2025·0 cites·20 claims
- 2460US11948832B2Bottom implant and airgap isolation for nanosheet semiconductor devicesAPPLIED MATERIALS INC·Filed 2021·Granted Apr 2, 2024·0 cites·19 claims
- 2560US8846476B2Methods of forming multiple N-type semiconductor devices with different threshold voltages on a semiconductor substrateGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 30, 2014·1 cites·31 claims
- 2660US2025194127A1High-temperature implant for gate-all-around devicesAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 2759US12463038B2Carbon and boron implantation for backside chemical mechanical planarization controlAPPLIED MATERIALS INC·Filed 2023·Granted Nov 4, 2025·0 cites·16 claims
- 2859US2025081592A1Contact resistance reduction for direct backside contactAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 2959US2025294832A1Contact formation for back side power distributionAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 3058US11626284B2Method of forming a 2-dimensional channel material, using ion implantationAPPLIED MATERIALS INC·Filed 2021·Granted Apr 11, 2023·0 cites·20 claims
- 3158US9231079B1Stress memorization techniques for transistor devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 5, 2016·1 cites·25 claims
- 3258US2025194072A1Implant for transistor bitline contact and junction formationAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3357US2024404887A1High-temperature implant for gate-all-around devicesAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3457US2025040186A1High-temperature implant for gate-all-around devicesAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3556US11778832B2Wordline contact formation in NAND devicesAPPLIED MATERIALS INC·Filed 2021·Granted Oct 3, 2023·0 cites·20 claims
- 3654US11424164B2Enhanced etch resistance for insulator layers implanted with low energy ionsAPPLIED MATERIALS INC·Filed 2020·Granted Aug 23, 2022·0 cites·19 claims
- 3753US10096488B2FinFET semiconductor structures and methods of fabricating sameGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 9, 2018·0 cites·14 claims
- 3852US9178053B2Transistor device with improved source/drain junction architecture and methods of making such a deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 3, 2015·0 cites·12 claims
- 3948US10692775B2Fin damage reduction during punch through implantation of FinFET deviceAPPLIED MATERIALS INC·Filed 2018·Granted Jun 23, 2020·0 cites·18 claims
- 4048US10686033B2Fin damage reduction during punch through implantation of FinFET deviceAPPLIED MATERIALS INC·Filed 2018·Granted Jun 16, 2020·0 cites·20 claims
- 4147US9373548B2CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layerPEI GEN·Filed 2008·Granted Jun 21, 2016·0 cites·3 claims
- 4247US2015348830A1Shallow trench isolationGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 4346US10510870B2Techniques for forming device having etch-resistant isolation oxideVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2018·Granted Dec 17, 2019·0 cites·17 claims
- 4445US2021119022A1Methods for forming ultra-shallow junctions having improved activationAPPLIED MATERIALS INC·Filed 2019·Application pending·0 cites
- 4544US10720357B2Method of forming transistor device having fin cut regionsVARIAN SEMICONDUCTOR EQUIPMENT ASS INC·Filed 2018·Granted Jul 21, 2020·0 cites·13 claims
- 4644US2015340501A1Forming independent-gate finfet with tilted pre-amorphization implantation and resulting deviceGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 4740US2015097197A1Finfet with sigma cavity with multiple epitaxial material regionsGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
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