Inventor · disambiguated record
George R. Mulfinger
Also filed as: MULFINGER GEORGE · MULFINGER GEORGE R · MULFINGER GEORGE ROBERT
33 granted patents·14 pending applications·106 citations·filing 2012–2024
95Inventor score
Top patents by PatentIndex Score
47 records- 0196US9917103B1Diffusion break forming after source/drain forming and related IC structureGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 13, 2018·26 cites·18 claims
- 0296US9812453B1Self-aligned sacrificial epitaxial capping for trench silicideGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 7, 2017·22 cites·14 claims
- 0394US9806170B1Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOIGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 31, 2017·12 cites·7 claims
- 0493US10396078B2Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 27, 2019·9 cites·16 claims
- 0593US10020307B1Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 10, 2018·9 cites·11 claims
- 0690US11798948B2Semiconductor structure with shared wellGLOBALFOUNDRIES US INC·Filed 2021·Granted Oct 24, 2023·2 cites·12 claims
- 0790US10043893B1Post gate silicon germanium channel condensation and method for producing the sameGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 7, 2018·5 cites·5 claims
- 0888US10008576B2Epi facet height uniformity improvement for FDSOI technologiesGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 26, 2018·5 cites·9 claims
- 0982US10522655B2Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOIGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 31, 2019·3 cites·7 claims
- 1081US10756184B2Faceted epitaxial source/drain regionsGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 25, 2020·3 cites·17 claims
- 1180US11031484B2Silicided gate structuresGLOBALFOUNDRIES US INC·Filed 2019·Granted Jun 8, 2021·2 cites·20 claims
- 1277US10825897B2Formation of enhanced faceted raised source/drain EPI material for transistor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 3, 2020·2 cites·14 claims
- 1377US10777642B2Formation of enhanced faceted raised source/drain epi material for transistor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Sep 15, 2020·2 cites·18 claims
- 1477US10217660B2Technique for patterning active regions of transistor elements in a late manufacturing stageGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 26, 2019·2 cites·20 claims
- 1577US2025046706A1Electronic fuses with a silicide layer having multiple thicknessesGLOBALFOUNDRIES SG PTE LTD·Filed 2024·Application pending·0 cites
- 1670US10741556B2Self-aligned sacrificial epitaxial capping for trench silicideGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 11, 2020·1 cites·12 claims
- 1769US12176351B2Photonics chips including a fully-depleted silicon-on-insulator field-effect transistorGLOBALFOUNDRIES US INC·Filed 2022·Granted Dec 24, 2024·0 cites·16 claims
- 1868US11569268B1Photonics chips including a fully-depleted silicon-on-insulator field-effect transistorGLOBALFOUNDRIES US INC·Filed 2021·Granted Jan 31, 2023·0 cites·18 claims
- 1968US9704971B2Epi facet height uniformity improvement for FDSOI technologiesGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 11, 2017·1 cites·10 claims
- 2067US12426315B2IC device with vertically-graded silicon germanium region adjacent device channel and method for formingGLOBALFOUNDRIES US INC·Filed 2023·Granted Sep 23, 2025·0 cites·20 claims
- 2166US12154854B2Electronic fuses with a silicide layer having multiple thicknessesGLOBALFOUNDRIES SG PTE LTD·Filed 2022·Granted Nov 26, 2024·0 cites·7 claims
- 2262US11217678B2Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOIGLOBALFOUNDRIES US INC·Filed 2019·Granted Jan 4, 2022·0 cites·20 claims
- 2355US10326007B2Post gate silicon germanium channel condensation and method for producing the sameGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 18, 2019·0 cites·11 claims
- 2455US2024128322A1Device with laterally graded channel regionGLOBALFOUNDRIES US INC·Filed 2022·Application pending·0 cites
- 2554US2024429237A1Semiconductor device including diffusion break structure and method of forming semiconductor deviceGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 2654US2025241062A1Structure with two work function metals over conductive bridge, and method to form sameGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 2753US11450573B2Structure with different stress-inducing isolation dielectrics for different polarity FETsGLOBALFOUNDRIES US INC·Filed 2020·Granted Sep 20, 2022·0 cites·18 claims
- 2852US2018315832A1Method for late differential soi thinning for improved fdsoi performance and hci optimizationGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 2951US11101364B2Field-effect transistors with diffusion blocking spacer sectionsGLOBALFOUNDRIES US INC·Filed 2019·Granted Aug 24, 2021·0 cites·20 claims
- 3050US11907685B2Structure and method for random code generationGLOBALFOUNDRIES US INC·Filed 2019·Granted Feb 20, 2024·0 cites·20 claims
- 3150US10680065B2Field-effect transistors with a grown silicon-germanium channelGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 9, 2020·0 cites·8 claims
- 3250US10050119B2Method for late differential SOI thinning for improved FDSOI performance and HCI optimizationGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 14, 2018·0 cites·11 claims
- 3350US2025006842A1Opening in stress-inducing liner(s) between transistorsGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 3449US11127843B2Asymmetrical lateral heterojunction bipolar transistorsGLOBALFOUNDRIES US INC·Filed 2020·Granted Sep 21, 2021·0 cites·20 claims
- 3549US11094805B2Lateral heterojunction bipolar transistors with asymmetric junctionsGLOBALFOUNDRIES US INC·Filed 2020·Granted Aug 17, 2021·0 cites·20 claims
- 3649US2023146952A1Transistor with faceted, raised source/drain regionGLOBALFOUNDRIES US INC·Filed 2021·Application pending·0 cites
- 3747US12446307B2Structure and method of forming spacers on unfaceted raised source/drain regionsGLOBALFOUNDRIES US INC·Filed 2022·Granted Oct 14, 2025·0 cites·20 claims
- 3847US2025126888A1Integrated circuit structure with diffusion break in p-type field effect transistor region and methodGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 3946US10236343B2Strain retention semiconductor member for channel SiGe layer of pFETGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 19, 2019·0 cites·12 claims
- 4044US2024188287A1One-time programmable fuse using pn junction over gate metal layer, and related methodGLOBALFOUNDRIES US INC·Filed 2022·Application pending·0 cites
- 4143US2020020770A1Composite spacers for tailoring the shape of the source and drain regions of a field-effect transistorGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 4242US10056381B2Punchthrough stop layers for fin-type field-effect transistorsGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 21, 2018·0 cites·20 claims
- 4342US2021091222A1Fin structures of finfet devicesGLOBALFOUNDRIES US INC·Filed 2019·Application pending·0 cites
- 4440US2019221483A1Single work function enablement for silicon nanowire deviceGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 4539US10388654B2Methods of forming a gate-to-source/drain contact structureGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 20, 2019·0 cites·20 claims
- 4639US2013032893A1Semiconductor device comprising metal gate electrode structures and non-fets with different height by early adaptation of gate stack topographyGLOBALFOUNDRIES INC·Filed 2012·Application pending·0 cites
- 4739US2019027370A1Shaped cavity for epitaxial semiconductor growthGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
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