Inventor · disambiguated record
Quang X. Mai
Also filed as: MAI QUANG · MAI QUANG X · MAI QUANG XUAN
11 granted patents·1 pending application·905 citations·filing 1997–2013
93Inventor score
Top patents by PatentIndex Score
12 records- 0198US6683380B2Integrated circuit with bonding layer over active circuitryTEXAS INSTRUMENTS INC·Filed 2002·Granted Jan 27, 2004·274 cites·11 claims
- 0297US7335536B2Method for fabricating low resistance, low inductance interconnections in high current semiconductor devicesTEXAS INSTRUMENTS INC·Filed 2005·Granted Feb 26, 2008·49 cites·14 claims
- 0396US6144100AIntegrated circuit with bonding layer over active circuitryTEXAS INSTRUMENTS INC·Filed 1997·Granted Nov 7, 2000·256 cites·17 claims
- 0494US6020640AThick plated interconnect and associated auxillary interconnectTEXAS INSTRUMENTS INC·Filed 1997·Granted Feb 1, 2000·174 cites·10 claims
- 0587US6025275AMethod of forming improved thick plated copper interconnect and associated auxiliary metal interconnectTEXAS INSTRUMENTS INC·Filed 1997·Granted Feb 15, 2000·90 cites·23 claims
- 0686US7413947B2Integrated high voltage capacitor having a top-level dielectric layer and a method of manufacture thereforTEXAS INSTRUMENTS INC·Filed 2006·Granted Aug 19, 2008·15 cites·18 claims
- 0778USRE46466EMethod for fabricating low resistance, low inductance interconnections in high current semiconductor devicesLANGE BERNHARD P·Filed 2010·Granted Jul 4, 2017·4 cites·30 claims
- 0863US6140702APlastic encapsulation for integrated circuits having plated copper top surface level interconnectTEXAS INSTRUMENTS INC·Filed 1997·Granted Oct 31, 2000·28 cites·12 claims
- 0956USRE48420EMethod for fabricating low resistance, low inductance interconnections in high current semiconductor devicesTEXAS INSTRUMENTS INC·Filed 2013·Granted Feb 2, 2021·0 cites·34 claims
- 1056USRE46618EMethod for fabricating low resistance, low inductance interconnections in high current semiconductor devicesTEXAS INSTRUMENTS INC·Filed 2013·Granted Nov 28, 2017·0 cites·30 claims
- 1150US6140150APlastic encapsulation for integrated circuits having plated copper top surface level interconnectTEXAS INSTRUMENTS INC·Filed 1999·Granted Oct 31, 2000·15 cites·10 claims
- 1237US2005151268A1Wafer-level assembly method for chip-size devices having flipped chipsFiled 2004·Application pending·0 cites
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