Inventor · disambiguated record
Christopher J. Penny
Also filed as: PENNY CHRISTOPHER J
167 granted patents·17 pending applications·2,087 citations·filing 2007–2024
99Inventor score
Top patents by PatentIndex Score
184 records- 0199US10229851B2Self-forming barrier for use in air gap formationIBM·Filed 2016·Granted Mar 12, 2019·317 cites·14 claims
- 0299US9837355B2Method for maximizing air gap in back end of the line interconnect through via landing modificationIBM·Filed 2016·Granted Dec 5, 2017·313 cites·5 claims
- 0399US9666528B1BEOL vertical fuse formed over air gapIBM·Filed 2016·Granted May 30, 2017·430 cites·14 claims
- 0499US9305836B1Air gap semiconductor structure with selective cap bilayerIBM·Filed 2014·Granted Apr 5, 2016·488 cites·10 claims
- 0598US11056429B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceTESSERA INC·Filed 2020·Granted Jul 6, 2021·4 cites·19 claims
- 0698US9934970B1Self aligned pattern formation post spacer etchback in tight pitch configurationsIBM·Filed 2017·Granted Apr 3, 2018·22 cites·13 claims
- 0798US9911651B1Skip-vias bypassing a metallization level at minimum pitchIBM·Filed 2016·Granted Mar 6, 2018·26 cites·16 claims
- 0898US9786760B1Air gap and air spacer pinch offIBM·Filed 2016·Granted Oct 10, 2017·22 cites·7 claims
- 0998US9349687B1Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnectIBM·Filed 2015·Granted May 24, 2016·96 cites·20 claims
- 1097US12218003B2Selective ILD deposition for fully aligned via with airgapADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 4, 2025·2 cites·20 claims
- 1197US11152257B2Barrier-less prefilled via formationIBM·Filed 2020·Granted Oct 19, 2021·5 cites·18 claims
- 1297US9991156B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2016·Granted Jun 5, 2018·15 cites·6 claims
- 1397US9966337B1Fully aligned via with integrated air gapsIBM·Filed 2017·Granted May 8, 2018·22 cites·12 claims
- 1497US9553019B1Airgap protection layer for via alignmentIBM·Filed 2016·Granted Jan 24, 2017·20 cites·20 claims
- 1597US9449871B1Hybrid airgap structure with oxide linerIBM·Filed 2015·Granted Sep 20, 2016·21 cites·10 claims
- 1696US9780027B2Hybrid airgap structure with oxide linerIBM·Filed 2016·Granted Oct 3, 2017·13 cites·18 claims
- 1796US9779944B1Method and structure for cut material selectionIBM·Filed 2016·Granted Oct 3, 2017·17 cites·19 claims
- 1895US11955424B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Apr 9, 2024·1 cites·20 claims
- 1995US11894265B2Top via with damascene line and viaIBM·Filed 2021·Granted Feb 6, 2024·2 cites·19 claims
- 2095US11574864B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceTESSERA LLC·Filed 2021·Granted Feb 7, 2023·2 cites·21 claims
- 2195US10109579B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceIBM·Filed 2018·Granted Oct 23, 2018·8 cites·20 claims
- 2294US11276639B2Conductive lines with subtractive cutsIBM·Filed 2020·Granted Mar 15, 2022·3 cites·18 claims
- 2394US11195795B1Well-controlled edge-to-edge spacing between adjacent interconnectsIBM·Filed 2020·Granted Dec 7, 2021·3 cites·20 claims
- 2494US10083905B2Skip-vias bypassing a metallization level at minimum pitchIBM·Filed 2017·Granted Sep 25, 2018·9 cites·19 claims
- 2594US9793193B1Air gap and air spacer pinch offIBM·Filed 2016·Granted Oct 17, 2017·7 cites·7 claims
- 2694US9685366B1Forming chamferless vias using thermally decomposable porefillerIBM·Filed 2016·Granted Jun 20, 2017·12 cites·11 claims
- 2793US10529569B2Self aligned pattern formation post spacer etchback in tight pitch configurationsIBM·Filed 2018·Granted Jan 7, 2020·5 cites·11 claims
- 2893US10366952B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceIBM·Filed 2018·Granted Jul 30, 2019·5 cites·17 claims
- 2993US10361157B2Method of manufacturing self-aligned interconnects by deposition of a non-conformal air-gap forming layer having an undulated upper surfaceIBM·Filed 2017·Granted Jul 23, 2019·6 cites·8 claims
- 3093US9837305B1Forming deep airgaps without flop overIBM·Filed 2016·Granted Dec 5, 2017·10 cites·20 claims
- 3192US9978560B2System and method for performing nano beam diffraction analysisIBM·Filed 2016·Granted May 22, 2018·6 cites·25 claims
- 3292US9793206B1Heterogeneous metallization using solid diffusion removal of metal interconnectsIBM·Filed 2016·Granted Oct 17, 2017·8 cites·10 claims
- 3392US9607886B1Self aligned conductive lines with relaxed overlayIBM·Filed 2016·Granted Mar 28, 2017·6 cites·20 claims
- 3492US8835305B2Method of fabricating a profile control in interconnect structuresYANG CHIH-CHAO·Filed 2012·Granted Sep 16, 2014·12 cites·13 claims
- 3591US10964588B2Selective ILD deposition for fully aligned via with airgapTESSERA INC·Filed 2020·Granted Mar 30, 2021·2 cites·17 claims
- 3691US9997451B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceIBM·Filed 2016·Granted Jun 12, 2018·5 cites·16 claims
- 3791US9711455B2Method of forming an air gap semiconductor structure with selective cap bilayerIBM·Filed 2015·Granted Jul 18, 2017·5 cites·12 claims
- 3890US10629529B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceTESSERA INC·Filed 2019·Granted Apr 21, 2020·3 cites·19 claims
- 3990US10242933B2Air gap and air spacer pinch offIBM·Filed 2017·Granted Mar 26, 2019·4 cites·20 claims
- 4089US11735524B2Electrical device having conductive lines with air gaps therebetween and interconnects without exclusion zonesIBM·Filed 2019·Granted Aug 22, 2023·3 cites·11 claims
- 4189US11189568B2Top via interconnect having a line with a reduced bottom dimensionIBM·Filed 2020·Granted Nov 30, 2021·2 cites·4 claims
- 4289US11171084B2Top via with next level line selective growthIBM·Filed 2020·Granted Nov 9, 2021·2 cites·14 claims
- 4389US11004790B2Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler materialIBM·Filed 2017·Granted May 11, 2021·4 cites·7 claims
- 4489US9786554B1Self aligned conductive linesIBM·Filed 2016·Granted Oct 10, 2017·5 cites·7 claims
- 4589US2025140606A1Selective ild deposition for fully aligned via with airgapADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 4689US2025062126A1Self aligned pattern formation post spacer etchback in tight pitch configurationsTESSERA LLC·Filed 2024·Application pending·0 cites
- 4788US11670510B2Self aligned pattern formation post spacer etchback in tight pitch configurationsTESSERA LLC·Filed 2021·Granted Jun 6, 2023·1 cites·18 claims
- 4888US11195792B2Top via stackIBM·Filed 2020·Granted Dec 7, 2021·2 cites·20 claims
- 4988US10256191B2Hybrid dielectric scheme for varying liner thickness and manganese concentrationIBM·Filed 2017·Granted Apr 9, 2019·4 cites·5 claims
- 5088US9960117B2Air gap semiconductor structure with selective cap bilayerIBM·Filed 2015·Granted May 1, 2018·4 cites·18 claims
Showing the top 50 of 184 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →