Inventor · disambiguated record
Heike Salz
Also filed as: SALZ HEIKE
12 granted patents·1 pending application·547 citations·filing 2006–2012
89Inventor score
Top patents by PatentIndex Score
13 records- 0197US7550396B2Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Jun 23, 2009·507 cites·22 claims
- 0283US7678690B2Semiconductor device comprising a contact structure with increased etch selectivityADVANCED MICRO DEVICES INC·Filed 2006·Granted Mar 16, 2010·12 cites·12 claims
- 0378US7416973B2Method of increasing the etch selectivity in a contact structure of semiconductor devicesADVANCED MICRO DEVICES INC·Filed 2006·Granted Aug 26, 2008·8 cites·10 claims
- 0476US8390127B2Contact trenches for enhancing stress transfer in closely spaced transistorsWEI ANDY·Filed 2009·Granted Mar 5, 2013·7 cites·22 claims
- 0574US7482219B2Technique for creating different mechanical strain by a contact etch stop layer stack with an intermediate etch stop layerADVANCED MICRO DEVICES INC·Filed 2006·Granted Jan 27, 2009·6 cites·21 claims
- 0667US7700377B2Method for reducing etch-induced process uniformities by omitting deposition of an endpoint detection layer during patterning of stressed overlayers in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2007·Granted Apr 20, 2010·2 cites·23 claims
- 0765US8034726B2Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materialsADVANCED MICRO DEVICES INC·Filed 2008·Granted Oct 11, 2011·3 cites·16 claims
- 0861US7608501B2Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stressADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 27, 2009·2 cites·13 claims
- 0955US8338314B2Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistorsRICHTER RALF·Filed 2009·Granted Dec 25, 2012·0 cites·16 claims
- 1050US2013095648A1Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistorsADVANCED MICRO DEVICES INC·Filed 2012·Application pending·0 cites
- 1144US7763507B2Stressed interlayer dielectric with reduced probability for void generation in a semiconductor device by using an intermediate etch control layer of increased thicknessGLOBALFOUNDRIES INC·Filed 2008·Granted Jul 27, 2010·0 cites·15 claims
- 1243US9006114B2Method for selectively removing a spacer in a dual stress liner approachFROHBERG KAI·Filed 2009·Granted Apr 14, 2015·0 cites·22 claims
- 1342US7883629B2Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategiesGLOBALFOUNDRIES INC·Filed 2007·Granted Feb 8, 2011·0 cites·18 claims
Join the waitlist — get patent alerts
Get an alert when Heike Salz files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →