Inventor · disambiguated record
Holger Schuehrer
Also filed as: SCHUEHRER HOLGER · SCHUEHRER HOLGER S
16 granted patents·2 pending applications·361 citations·filing 2005–2019
92Inventor score
Files withADVANCED MICRO DEVICES INC5GLOBALFOUNDRIES INC5RICHTER RALF3SCHUEHRER HOLGER2FROHBERG KAI1
Top patents by PatentIndex Score
18 records- 0197US7259091B2Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layerADVANCED MICRO DEVICES INC·Filed 2005·Granted Aug 21, 2007·268 cites·10 claims
- 0293US7396718B2Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stressADVANCED MICRO DEVICES INC·Filed 2005·Granted Jul 8, 2008·29 cites·9 claims
- 0388US7491555B2Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2006·Granted Feb 17, 2009·17 cites·19 claims
- 0485US7410885B2Method of reducing contamination by removing an interlayer dielectric from the substrate edgeADVANCED MICRO DEVICES INC·Filed 2006·Granted Aug 12, 2008·12 cites·12 claims
- 0582US8951907B2Semiconductor devices having through-contacts and related fabrication methodsRICHTER RALF·Filed 2010·Granted Feb 10, 2015·7 cites·18 claims
- 0674US8426312B2Method of reducing contamination by providing an etch stop layer at the substrate edgeRICHTER RALF·Filed 2006·Granted Apr 23, 2013·5 cites·10 claims
- 0773US7781343B2Semiconductor substrate having a protection layer at the substrate back sideGLOBALFOUNDRIES INC·Filed 2007·Granted Aug 24, 2010·6 cites·20 claims
- 0871US8129276B2Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistorsRICHTER RALF·Filed 2010·Granted Mar 6, 2012·3 cites·11 claims
- 0970US8384161B2Contact optimization for enhancing stress transfer in closely spaced transistorsGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 26, 2013·3 cites·26 claims
- 1069US7820536B2Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layerADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 26, 2010·3 cites·19 claims
- 1166US7638424B2Technique for non-destructive metal delamination monitoring in semiconductor devicesGLOBALFOUNDRIES INC·Filed 2006·Granted Dec 29, 2009·3 cites·19 claims
- 1258US8212346B2Method and apparatus for reducing semiconductor package tensile stressRYAN E TODD·Filed 2008·Granted Jul 3, 2012·2 cites·9 claims
- 1358US8039400B2Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier depositionGLOBALFOUNDRIES INC·Filed 2009·Granted Oct 18, 2011·1 cites·25 claims
- 1455US8097536B2Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layerSCHUEHRER HOLGER·Filed 2009·Granted Jan 17, 2012·2 cites·14 claims
- 1546US7763476B2Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffractionGLOBALFOUNDRIES INC·Filed 2007·Granted Jul 27, 2010·0 cites·7 claims
- 1642US11127674B2Back end of the line metal structure and methodGLOBALFOUNDRIES US INC·Filed 2019·Granted Sep 21, 2021·0 cites·20 claims
- 1741US2006246718A1Technique for forming self-aligned vias in a metallization layerFROHBERG KAI·Filed 2005·Application pending·0 cites
- 1834US2006141775A1Method of forming electrical connections in a semiconductor structureSCHUEHRER HOLGER·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →