Inventor · disambiguated record
Huai Huang
Also filed as: HUANG HUAI · HUANG HUAI AN
50 granted patents·23 pending applications·175 citations·filing 2007–2024
98Inventor score
Top patents by PatentIndex Score
73 records- 0198US11056429B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceTESSERA INC·Filed 2020·Granted Jul 6, 2021·4 cites·19 claims
- 0298US9911651B1Skip-vias bypassing a metallization level at minimum pitchIBM·Filed 2016·Granted Mar 6, 2018·26 cites·16 claims
- 0397US12218003B2Selective ILD deposition for fully aligned via with airgapADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 4, 2025·2 cites·20 claims
- 0497US11756887B2Backside floating metal for increased capacitanceIBM·Filed 2021·Granted Sep 12, 2023·5 cites·22 claims
- 0597US11152257B2Barrier-less prefilled via formationIBM·Filed 2020·Granted Oct 19, 2021·5 cites·18 claims
- 0697US9966337B1Fully aligned via with integrated air gapsIBM·Filed 2017·Granted May 8, 2018·22 cites·12 claims
- 0796US10777411B1Semiconductor device with selective dielectric depositionIBM·Filed 2019·Granted Sep 15, 2020·20 cites·18 claims
- 0895US11955424B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Apr 9, 2024·1 cites·20 claims
- 0995US11574864B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceTESSERA LLC·Filed 2021·Granted Feb 7, 2023·2 cites·21 claims
- 1095US10109579B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceIBM·Filed 2018·Granted Oct 23, 2018·8 cites·20 claims
- 1194US11944013B2Magnetic tunnel junction device with minimum stray fieldIBM·Filed 2021·Granted Mar 26, 2024·3 cites·9 claims
- 1294US10083905B2Skip-vias bypassing a metallization level at minimum pitchIBM·Filed 2017·Granted Sep 25, 2018·9 cites·19 claims
- 1394US9685366B1Forming chamferless vias using thermally decomposable porefillerIBM·Filed 2016·Granted Jun 20, 2017·12 cites·11 claims
- 1493US10366952B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceIBM·Filed 2018·Granted Jul 30, 2019·5 cites·17 claims
- 1593US9837305B1Forming deep airgaps without flop overIBM·Filed 2016·Granted Dec 5, 2017·10 cites·20 claims
- 1692US9793206B1Heterogeneous metallization using solid diffusion removal of metal interconnectsIBM·Filed 2016·Granted Oct 17, 2017·8 cites·10 claims
- 1791US10964588B2Selective ILD deposition for fully aligned via with airgapTESSERA INC·Filed 2020·Granted Mar 30, 2021·2 cites·17 claims
- 1891US9997451B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceIBM·Filed 2016·Granted Jun 12, 2018·5 cites·16 claims
- 1990US10629529B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceTESSERA INC·Filed 2019·Granted Apr 21, 2020·3 cites·19 claims
- 2089US12424549B2Skip-level TSV with hybrid dielectric scheme for backside power deliveryIBM·Filed 2022·Granted Sep 23, 2025·1 cites·15 claims
- 2189US2025140606A1Selective ild deposition for fully aligned via with airgapADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 2287US11244861B2Method and structure for forming fully-aligned viaIBM·Filed 2020·Granted Feb 8, 2022·2 cites·20 claims
- 2387US10763160B1Semiconductor device with selective insulator for improved capacitanceIBM·Filed 2019·Granted Sep 1, 2020·5 cites·17 claims
- 2487US10529662B2Method and structure to construct cylindrical interconnects to reduce resistanceIBM·Filed 2018·Granted Jan 7, 2020·3 cites·10 claims
- 2587US9960078B1Reflow interconnect using RuIBM·Filed 2017·Granted May 1, 2018·4 cites·15 claims
- 2682US9837485B2High-density MIM capacitorsIBM·Filed 2016·Granted Dec 5, 2017·3 cites·18 claims
- 2781US11158543B2Silicide formation for source/drain contact in a vertical transport field-effect transistorIBM·Filed 2019·Granted Oct 26, 2021·2 cites·11 claims
- 2876US10361117B2Selective ILD deposition for fully aligned via with airgapIBM·Filed 2017·Granted Jul 23, 2019·1 cites·13 claims
- 2976US9824982B1Structure and fabrication method for enhanced mechanical strength crack stopIBM·Filed 2016·Granted Nov 21, 2017·2 cites·11 claims
- 3075US11676854B2Selective ILD deposition for fully aligned via with airgapTESSERA LLC·Filed 2021·Granted Jun 13, 2023·0 cites·20 claims
- 3169US11621189B2Barrier-less prefilled via formationIBM·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 3266US10784197B2Method and structure to construct cylindrical interconnects to reduce resistanceIBM·Filed 2019·Granted Sep 22, 2020·0 cites·18 claims
- 3365US12334442B2Dielectric caps for power and signal line routingIBM·Filed 2022·Granted Jun 17, 2025·0 cites·20 claims
- 3465US11621199B2Silicide formation for source/drain contact in a vertical transport field-effect transistorIBM·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 3565US10943866B2Method and structure to construct cylindrical interconnects to reduce resistanceIBM·Filed 2019·Granted Mar 9, 2021·0 cites·20 claims
- 3665US10651078B2Selective ILD deposition for fully aligned via with airgapTESSERA INC·Filed 2019·Granted May 12, 2020·0 cites·18 claims
- 3765US2025096036A1Selective deposition of graphene on cobalt-capped copper dual damascene interconnectLAM RES CORP·Filed 2022·Application pending·0 cites
- 3863US12494428B2Airgap spacer for power viaIBM·Filed 2022·Granted Dec 9, 2025·0 cites·17 claims
- 3963US12424557B2Dual structured buried railIBM·Filed 2022·Granted Sep 23, 2025·0 cites·20 claims
- 4063US2022013406A1Trapezoidal Interconnect at Tight BEOL PitchIBM·Filed 2021·Application pending·0 cites
- 4162US12412836B2Backside power planeIBM·Filed 2022·Granted Sep 9, 2025·0 cites·14 claims
- 4259US2025096127A1Backside fuse structure utilizing backside contactIBM·Filed 2023·Application pending·0 cites
- 4358US11177162B2Trapezoidal interconnect at tight BEOL pitchIBM·Filed 2019·Granted Nov 16, 2021·0 cites·21 claims
- 4458US10217664B2Reflow interconnect using RuIBM·Filed 2018·Granted Feb 26, 2019·0 cites·20 claims
- 4558US10211101B2Reflow interconnect using RuIBM·Filed 2017·Granted Feb 19, 2019·0 cites·18 claims
- 4658US2024421088A1Power distribution with backside power planesIBM·Filed 2023·Application pending·0 cites
- 4757US12261056B2Top via patterning using metal as hard mask and via conductorIBM·Filed 2021·Granted Mar 25, 2025·0 cites·8 claims
- 4857US2024332165A1Offset via formation for flexible routingIBM·Filed 2023·Application pending·0 cites
- 4957US2024321687A1Backside decoupling capacitor integration with backside contactIBM·Filed 2023·Application pending·0 cites
- 5057US2024321630A1Top via interconnectIBM·Filed 2023·Application pending·0 cites
Showing the top 50 of 73 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →