Inventor · disambiguated record
Martin Mazur
Also filed as: MAZUR MARTIN
17 granted patents·3 pending applications·602 citations·filing 2001–2016
93Inventor score
Top patents by PatentIndex Score
20 records- 0197US7550396B2Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Jun 23, 2009·507 cites·22 claims
- 0293US7314793B2Technique for controlling mechanical stress in a channel region by spacer removalADVANCED MICRO DEVICES INC·Filed 2005·Granted Jan 1, 2008·39 cites·14 claims
- 0388US7981740B2Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterningGLOBALFOUNDRIES INC·Filed 2010·Granted Jul 19, 2011·13 cites·21 claims
- 0487US8927407B2Method of forming self-aligned contacts for a semiconductor deviceBAARS PETER·Filed 2012·Granted Jan 6, 2015·9 cites·19 claims
- 0584US8258062B2Cap layer removal in a high-K metal gate stack by using an etch processRICHTER RALF·Filed 2010·Granted Sep 4, 2012·8 cites·25 claims
- 0673US9972634B2Semiconductor device comprising a floating gate flash memory deviceGLOBALFOUNDRIES INC·Filed 2016·Granted May 15, 2018·2 cites·20 claims
- 0766US7938973B2Arc layer having a reduced flaking tendency and a method of manufacturing the sameADVANCED MICRO DEVICES INC·Filed 2007·Granted May 10, 2011·2 cites·20 claims
- 0866US7887978B2Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditionsGLOBALFOUNDRIES INC·Filed 2008·Granted Feb 15, 2011·2 cites·15 claims
- 0961US7994059B2Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Aug 9, 2011·2 cites·9 claims
- 1060US6936383B2Method of defining the dimensions of circuit elements by using spacer deposition techniquesADVANCED MICRO DEVICES INC·Filed 2002·Granted Aug 30, 2005·8 cites·20 claims
- 1159US8716120B2High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technologyHEMPEL KLAUS·Filed 2012·Granted May 6, 2014·1 cites·21 claims
- 1258US9372392B2Reticles for use in forming implant masking layers and methods of forming implant masking layersGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 21, 2016·0 cites·20 claims
- 1358US6649525B1Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing processADVANCED MICRO DEVICES INC·Filed 2002·Granted Nov 18, 2003·7 cites·15 claims
- 1445US7547561B2Advanced process control model incorporating a target offset termADVANCED MICRO DEVICES INC·Filed 2005·Granted Jun 16, 2009·0 cites·7 claims
- 1542US8802360B2Reticles for use in forming implant masking layers and methods of forming implant masking layersMAZUR MARTIN·Filed 2012·Granted Aug 12, 2014·0 cites·8 claims
- 1641US6759179B1Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing processADVANCED MICRO DEVICES INC·Filed 2002·Granted Jul 6, 2004·2 cites·14 claims
- 1741US2006172518A1Method of patterning a layer of a materialFROHBERG KAI·Filed 2005·Application pending·0 cites
- 1838US2005233532A1Method of forming sidewall spacersLENSKI MARKUS·Filed 2005·Application pending·0 cites
- 1937US9281200B2Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate dopingTHEES HANS-JUERGEN·Filed 2011·Granted Mar 8, 2016·0 cites·22 claims
- 2036US2002076843A1Semiconductor structure having a silicon oxynitride ARC layer and a method of forming the sameFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →